Ctrl_Reg (FUNNEL3P) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

Ctrl_Reg (FUNNEL3P) Register Description

Register NameCtrl_Reg
Offset Address0x0000000000
Absolute Address 0x00FE910000 (CORESIGHT_SOC_FUNN_0)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionSoc_dbug_lpd
Funnel Control

Register enables the slave ports and defines the hold time of the slave ports. Hold time refers to the number of transactions that are output on the funnel master port from the same slave while that slave port atvalidsx is HIGH. Hold time does not refer to clock cycles in this context

Ctrl_Reg (FUNNEL3P) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
HT11:8rwNormal read/write0x0The formatting scheme can easily become inefficient if fast switching occurs, so, where possible, this must be minimized. If a source has nothing to transmit, then another source is selected irrespective of the minimum number of transactions. The ATB Funnel holds for the minimum hold time and one additional cycle.
The maximum value that can be entered is 0xE and this equates to 15 cycles.
0xF is reserved.
EnS2 2rwNormal read/write0x0Reserved, set = 0.
EnS1 1rwNormal read/write0x0Funnel input port 1 control (RPU core1):
0: disable, port is disabled from priority selection scheme (default).
1: enable.
EnS0 0rwNormal read/write0x0Funnel input port 0 control (RPU core0):
0: disable, port is disabled from priority selection scheme (default).
1: enable.