Ctrl_Reg (FUNNEL4P) Register Description
| Register Name | Ctrl_Reg |
|---|---|
| Offset Address | 0x0000000000 |
| Absolute Address |
0x00FE920000 (CORESIGHT_SOC_FUNN_1) 0x00FE930000 (CORESIGHT_SOC_FUNN_2) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | The Funnel Control Register enables the slave ports and defines the hold time of the slave ports. Hold time refers to the number of transactions that are output on the funnel master port from the same slave while that slave port atvalidsx is HIGH. Hold time does not refer to clock cycles in this context |
Ctrl_Reg (FUNNEL4P) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| HT | 11:8 | rwNormal read/write | 0x0 | The formatting scheme can easily become inefficient if fast switching occurs, so, where possible, this must be minimized. If a source has nothing to transmit, then another source is selected irrespective of the minimum number of transactions. The ATB Funnel holds for the minimum hold time and one additional cycle. The maximum value that can be entered is 0xE and this equates to 15 cycles. 0xF is reserved. |
| EnS3 | 3 | rwNormal read/write | 0x0 | Setting this bit enables this input, or slave, port. If the bit is not set then this has the effect of excluding the port from the priority selection scheme. The reset value is all clear, that is, all ports disabled. |
| EnS2 | 2 | rwNormal read/write | 0x0 | Setting this bit enables this input, or slave, port. If the bit is not set then this has the effect of excluding the port from the priority selection scheme. The reset value is all clear, that is, all ports disabled. |
| EnS1 | 1 | rwNormal read/write | 0x0 | Setting this bit enables this input, or slave, port. If the bit is not set then this has the effect of excluding the port from the priority selection scheme. The reset value is all clear, that is, all ports disabled. |
| EnS0 | 0 | rwNormal read/write | 0x0 | Setting this bit enables this input, or slave, port. If the bit is not set then this has the effect of excluding the port from the priority selection scheme. The reset value is all clear, that is, all ports disabled. |