Current_test_pattern_mode (TPIU) Register Description
| Register Name | Current_test_pattern_mode |
|---|---|
| Offset Address | 0x0000000204 |
| Absolute Address | 0x00FE980204 (CORESIGHT_SOC_TPIU) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | This register indicates the current test pattern/mode selected. Only one of the modes can be set, using bits 17-16, but a multiple number of bits for the patterns can be set using bits 3-0. If Timed Mode is chosen, then after the allotted number of cycles has been reached, the mode automatically switches to Off Mode. On reset this register is set to 18h00000, Off Mode with no selected patterns. |
Current_test_pattern_mode (TPIU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| PCONTEN | 17 | rwNormal read/write | 0x0 | Indicates whether Continuous Mode is enabled. |
| PTIMEEN | 16 | rwNormal read/write | 0x0 | Indicates whether Timed Mode is enabled. |
| PATF0 | 3 | rwNormal read/write | 0x0 | FF/00 pattern enabled to be output over the Trace Port. |
| PATA5 | 2 | rwNormal read/write | 0x0 | AA/55 pattern enabled to be output over the Trace Port. |
| PATW0 | 1 | rwNormal read/write | 0x0 | Walking 0s Pattern enabled to be output over the Trace Port. |
| PATW1 | 0 | rwNormal read/write | 0x0 | Walking 1s Pattern enabled to be output over the Trace Port. |