DBG1 (DDRC) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DBG1 (DDRC) Register Description

Register NameDBG1
Offset Address0x0000000304
Absolute Address 0x00FD070304 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionDebug Register 1

This register is dynamic. Dynamic registers can be written at any time during operation.

DBG1 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
dis_hif 1rwNormal read/write0x0When 1, DDRC asserts the HIF command signal hif_cmd_stall. DDRC will ignore the hif_cmd_valid and all other associated request signals.
This bit is intended to be switched on-the-fly.
dis_dq 0rwNormal read/write0x0When 1, DDRC will not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted.
This bit may be used to prevent reads or writes being issued by the DDRC, which makes it safe to modify certain register fields associated with reads and writes (see User Guide for details).
After setting this bit, it is strongly recommended to poll DBGCAM.wr_data_pipeline_empty and DBGCAM.rd_data_pipeline_empty, before making changes to any registers which affect reads and writes.
This will ensure that the relevant logic in the DDRC is idle.
This bit is intended to be switched on-the-fly.