DBGBCR5_EL1 (A53_DBG_2) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DBGBCR5_EL1 (A53_DBG_2) Register Description

Register NameDBGBCR5_EL1
Offset Address0x0000000458
Absolute Address 0x00FEE10458 (CORESIGHT_A53_DBG_2)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionDebug Breakpoint Control Registers

DBGBCR5_EL1 (A53_DBG_2) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
BT23:20rwNormal read/write0Breakpoint Type. Possible values are:The field breaks down as follows:BT[3:1]: Base type.000Match address. DBGBVR<n>_EL1 is the address of an instruction.010Mismatch address. Behaves as type 0b000 if in an AArch64 translation, or if halting debug-mode is enabled and halting is allowed. Otherwise, DBGBVR<n>_EL1 is the address of an instruction to be stepped.001Match context ID. DBGBVR<n>_EL1[31:0] is a context ID.100Match VMID. DBGBVR<n>_EL1[39:32] is a VMID.101Match VMID and context ID. DBGBVR<n>_EL1[31:0] is a context ID, and DBGBVR<n>_EL1[39:32] is a VMID.BT[0]: Enable linking.If the breakpoint is not context-aware, BT[3] and BT[1] are RES0. If EL2 is not implemented, BT[3] is RES0. If EL1 using AArch32 is not implemented, BT[2] is RES0.The values 011x and 11xx are reserved, but must behave as if the breakpoint is disabled. Software must not rely on this property as the behavior of reserved values might change in a future revision of the architecture.
LBN19:16rwNormal read/write0Linked breakpoint number. For Linked address matching breakpoints, this specifies the index of the Context-matching breakpoint linked to.
SSC15:14rwNormal read/write0Security state control. Determines the security states under which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the HMC and PMC fields.
HMC13rwNormal read/write0Higher mode control. Determines the debug perspective for deciding when a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and PMC fields.
BAS 8:5rwNormal read/write0Byte address select. Defines which half-words an address-matching breakpoint matches, regardless of the instruction set and execution state. In an AArch64-only implementation, this field is reserved, RES1. Otherwise:BAS[2] and BAS[0] are read/write.BAS[3] and BAS[1] are read-only copies of BAS[2] and BAS[0] respectively.The values 0b0011 and 0b1100 are only supported if AArch32 is supported at any exception level.The permitted values depend on the breakpoint type.For Address match breakpoints in either AArch32 or AArch64 state:BASMatch instruction atConstraint for debuggers0b0011DBGBVR<n>_EL1Use for T32 and T32EE instructions.0b1100DBGBVR<n>_EL1+2Use for T32 and T32EE instructions.0b1111DBGBVR<n>_EL1Use for A64 and A32 instructions.0b0000 is reserved and must behave as if the breakpoint is disabled or map to a permitted value.For Address mismatch breakpoints in an AArch32 stage 1 translation regime:BASStep instruction atConstraint for debuggers0b0000-Use for a match anywhere breakpoint.0b0011DBGBVR<n>_EL1Use for stepping T32 and T32EE instructions.0b1100DBGBVR<n>_EL1+2Use for stepping T32 and T32EE instructions.0b1111DBGBVR<n>_EL1Use for stepping A64 and A32 instructions.For Context matching breakpoints, this field is RES1 and ignored.
PMC 2:1rwNormal read/write0Privilege mode control. Determines the exception level or levels at which a breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and HMC fields.
E 0rwNormal read/write0Enable breakpoint DBGBVR<n>_EL1. Possible values are: