DBGSTAT (DDRC) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DBGSTAT (DDRC) Register Description

Register NameDBGSTAT
Offset Address0x0000000310
Absolute Address 0x00FD070310 (DDRC)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionStatus Debug Register

DBGSTAT (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ctrlupd_busy 5roRead-only0x0SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the DDRC accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the DDRC. It is recommended not to perform ctrlupd operations when this signal is high.
- 0 - Indicates that the SoC core can initiate a ctrlupd operation
- 1 - Indicates that ctrlupd operation has not been initiated yet in the DDRC
zq_calib_short_busy 4roRead-only0x0SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the DDRC accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the DDRC. It is recommended not to perform ZQCS operations when this signal is high.
- 0 - Indicates that the SoC core can initiate a ZQCS operation
- 1 - Indicates that ZQCS operation has not been initiated yet in the DDRC
rank1_refresh_busy 1roRead-only0x0SoC core may initiate a rank1_refresh operation (refresh operation to rank 1) only if this signal is low. This signal goes high in the clock after DBGCMD.rank1_refresh is set to one. It goes low when the rank1_refresh operation is stored in the DDRC. It is recommended not to perform rank1_refresh operations when this signal is high.
- 0 - Indicates that the SoC core can initiate a rank1_refresh operation
- 1 - Indicates that rank1_refresh operation has not been stored yet in the DDRC
rank0_refresh_busy 0roRead-only0x0SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in the DDRC. It is recommended not to perform rank0_refresh operations when this signal is high.
- 0 - Indicates that the SoC core can initiate a rank0_refresh operation
- 1 - Indicates that rank0_refresh operation has not been stored yet in the DDRC