DBG_LPD_CTRL (CRL_APB) Register Description
| Register Name | DBG_LPD_CTRL |
|---|---|
| Offset Address | 0x00000000B0 |
| Absolute Address | 0x00FF5E00B0 (CRL_APB) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x01002000 |
| Description | Debug Clock Generator Config in LPD |
DBG_LPD_CTRL (CRL_APB) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:25 | rwNormal read/write | 0x0 | reserved |
| CLKACT | 24 | rwNormal read/write | 0x1 | Clock active control. 0: disable. Clock stop. 1: enable. |
| Reserved | 23:14 | rwNormal read/write | 0x0 | reserved |
| DIVISOR0 | 13:8 | rwNormal read/write | 0x20 | 6-bit divider. |
| Reserved | 7:3 | rwNormal read/write | 0x0 | reserved |
| SRCSEL | 2:0 | rwNormal read/write | 0x0 | Clock generator input source. 000: RPLL 010: IOPLL 011: DPLL_CLK_TO_LPD |