DBG_TSTMP_CTRL (CRF_APB) Register Description
| Register Name | DBG_TSTMP_CTRL |
|---|---|
| Offset Address | 0x00000000F8 |
| Absolute Address | 0x00FD1A00F8 (CRF_APB) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000A00 |
| Description | Debug Time Stamp Clock Generator Control in FPD. |
DBG_TSTMP_CTRL (CRF_APB) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 24 | rwNormal read/write | 0x0 | reserved - clock active is controlled by DBG_FPD_CTRL [CLKACT] (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware. |
| DIVISOR0 | 13:8 | rwNormal read/write | 0xA | 6-bit divider. |
| SRCSEL | 2:0 | rwNormal read/write | 0x0 | Clock generator input source. 000: IOPLL_TO_FPD 010: DPLL 011: APLL |