DBICTL (DDRC) Register Description
| Register Name | DBICTL |
|---|---|
| Offset Address | 0x00000001C0 |
| Absolute Address | 0x00FD0701C0 (DDRC) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000001 |
| Description | DM/DBI Control Register |
All register fields are quasi-dynamic group 1, unless described otherwise in the register field description. Group 1 registers can be written when no read/write traffic is present at the DFI.
DBICTL (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| rd_dbi_en | 2 | rwNormal read/write | 0x0 | Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read DBI is enabled. This signal must be set the same value as DRAMs mode register. - DDR4: MR5 bit A12. - LPDDR4: MR3[6] |
| wr_dbi_en | 1 | rwNormal read/write | 0x0 | Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Write DBI is enabled. This signal must be set the same value as DRAMs mode register. - DDR4: MR5 bit A11. - LPDDR4: MR3[7] |
| dm_en | 0 | rwNormal read/write | 0x1 | DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. This signal must be set the same logical value as DRAMs mode register. - DDR4: Set this to same value as MR5 bit A10. - LPDDR4: Set this to inverted value of MR13[5] which is opposite polarity from this signal Programming Mode: Quasi-dynamic Group 3 |