DCR (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DCR (DDR_PHY) Register Description

Register NameDCR
Offset Address0x0000000100
Absolute Address 0x00FD080100 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x0000040D
DescriptionDRAM Configuration Register

DCR (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
GEARDN31rwNormal read/write0x0DDR4 Gear Down timing
If set, the PUB will generate AC bus signals to the SDRAM with a
modified 2-cycle (2T) timing, lining the signals with the rising edge of
the SDRAM clock instead of in quadrature to it.
Note: This BIST should be programmed to 1b0 during AC BIST
loopback
UBG30rwNormal read/write0x0Un-used Bank Group: Indicates if set that BG[1] pin of PHY is unused
and not connected to the memory (for example, UDIMM x16). In such
scenario, Output Enable for BG[1] IO may be disabled from
ACIOCR3.BGOEMODE register field.
UDIMM29rwNormal read/write0x0Un-buffered DIMM Address Mirroring: Indicates if set that there is
address mirroring on the second rank of an un-buffered DIMM (the
rank connected to CS#[1]). In this case, the PUB re-scrambles the
bank and address when sending mode register commands to the
second rank. This only applies to PUB internal SDRAM transactions.
Transactions generated by the controller must make its own
adjustments when using an un-buffered DIMM. DCR[NOSRA] must be
set if address mirroring is enabled.
DDR2T28rwNormal read/write0x0DDR 2T Timing: Indicates if set that 2T timing should be used by PUB
internally generated SDRAM transactions.
This bit should be programmed to '0' during AC
BIST loopback.
NOSRA27rwNormal read/write0x0No Simultaneous Rank Access: Specifies if set that simultaneous rank
access on the same clock cycle is not allowed. This means that
multiple chip select signals should not be asserted at the same time.
This may be required on some DIMM systems.
Note: This is not supported in LPDDR4 mode
Reserved26:18roRead-only0x0Return zeroes on reads.
BYTEMASK17:10rwNormal read/write0x1Byte Mask: Mask applied to all beats of read data on all bytes lanes
during read DQS gate training. This allows training to be conducted
based on selected bit(s) from the byte lanes. Note that this mask
applies in DDR3 MPR operation mode as well and must be in keeping
with the PDQ field setting above.
DDRTYPE 9:8rwNormal read/write0x0DDR Type: Selects the DDR type for the specified DDR mode.
00 = All DRAM types
01, 10, 11 = RESERVED
MPRDQ 7rwNormal read/write0x0Multi-Purpose Register (MPR) DQ: Specifies the value that is driven
on non-primary DQ pins during MPR reads. Valid values are:
0 = Primary DQ drives out the data from MPR (0-1-0-1); non-
primary DQs drive '0'1 = Primary DQ and non-primary DQs all drive the same data from
MPR (0-1-0-1)
Note: DDR4 and DDR3 only
PDQ 6:4rwNormal read/write0x0Primary DQ: Specifies the DQ pin in a byte that is designated as a
primary pin for Multi-Purpose Register (MPR) reads. Valid values are 0
to 7 for DQ[0] to DQ[7] respectively.
Note: DDR4 and DDR3 only
DDR8BNK 3rwNormal read/write0x1DDR 8-Bank: Indicates if set that the SDRAM used has 8 banks. tRPA
= tRP+1 and tFAW are used for 8-bank DRAMs, other tRPA = tRP and no
tFAW is used. Note that a setting of 1 for DRAMs that have fewer than 8
banks still results in correct functionality but less tighter DRAM
command spacing for the parameters described here.
DDRMD 2:0rwNormal read/write0x5DDR Mode: SDRAM DDR mode. Valid values are:
000 = RESERVED
001 = LPDDR3
010 = RESERVED
011 = DDR3
100 = DDR4
101 = LPDDR4
111 = RESERVED