DCUAR (DDR_PHY) Register Description
| Register Name | DCUAR |
|---|---|
| Offset Address | 0x0000000300 |
| Absolute Address | 0x00FD080300 (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | DCU Address Register |
DCUAR (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:20 | roRead-only | 0x0 | Reserved. Return zeros on reads. |
| CSADDR_R | 19:16 | rwNormal read/write | 0x0 | Cache Slice Address: Address of the cache slice to be read. |
| CWADDR_R | 15:12 | rwNormal read/write | 0x0 | Cache Word Address: Address of the cache word to be read. |
| ATYPE | 11 | rwNormal read/write | 0x0 | Access Type: Specifies the type of access to be performed using this address. Valid values are: 0 = Write access 1 = Read access |
| INCA | 10 | rwNormal read/write | 0x0 | Increment Address: Specifies, if set, that the cache address specified in CWADDR and CSADDR should be automatically incremented after each access of the cache. The increment happens in such a way that all the slices of a selected word are first accessed before going to the next word. |
| CSEL | 9:8 | rwNormal read/write | 0x0 | Cache Select: Selects the cache to be accessed. Valid values are: 00 = Command cache 01 = Expected data cache 10 = Read data cache 11 = RESERVED |
| CSADDR_W | 7:4 | rwNormal read/write | 0x0 | Cache Slice Address: Address of the cache slice to be written. |
| CWADDR_W | 3:0 | rwNormal read/write | 0x0 | Cache Word Address: Address of the cache word to be written. |