DCULR (DDR_PHY) Register Description
| Register Name | DCULR |
|---|---|
| Offset Address | 0x000000030C |
| Absolute Address | 0x00FD08030C (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0xF0000000 |
| Description | DCU Loop Register |
DCULR (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| XLEADDR | 31:28 | rwNormal read/write | 0xF | Expected Data Loop End Address: The last expected data cache word address that contains valid expected data. Expected data should looped between 0 and this address. |
| Reserved | 27:18 | roRead-only | 0x0 | Reserved. Return zeros on reads. |
| IDA | 17 | rwNormal read/write | 0x0 | Increment DRAM Address: Indicates if set that DRAM addresses should be incremented every time a DRAM read/write command inside the loop is executed. |
| LINF | 16 | rwNormal read/write | 0x0 | Loop Infinite: Indicates if set that the loop should be executed indefinitely until stopped by the STOP command. Otherwise the loop is execute LCNT times. |
| LCNT | 15:8 | rwNormal read/write | 0x0 | Loop Count: The number of times that the loop should be executed if LINF is not set. |
| LEADDR | 7:4 | rwNormal read/write | 0x0 | Loop End Address: Command cache word address where the loop should end. |
| LSADDR | 3:0 | rwNormal read/write | 0x0 | Loop Start Address: Command cache word address where the loop should start. |