DCURR (DDR_PHY) Register Description
| Register Name | DCURR |
|---|---|
| Offset Address | 0x0000000308 |
| Absolute Address | 0x00FD080308 (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | DCU Run Register |
DCURR (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:24 | roRead-only | 0x0 | Reserved. Return zeros on reads. |
| XCEN | 23 | rwNormal read/write | 0x0 | Expected Compare Enable: Indicates if set that read data coming back from the SDRAM should be should be compared with the expected data. |
| RCEN | 22 | rwNormal read/write | 0x0 | Read Capture Enable: Indicates if set that read data coming back from the SDRAM should be captured into the read data cache. |
| SCOF | 21 | rwNormal read/write | 0x0 | Stop Capture On Full: Specifies if set that the capture of read data should stop when the capture cache is full. |
| SONF | 20 | rwNormal read/write | 0x0 | Stop On Nth Fail: Specifies if set that the execution of commands and the capture of read data should stop when there are N read data failures. The number of failures is specified by NFAIL. Otherwise commands execute until the end of the program or until manually stopped using a STOP command. |
| NFAIL | 19:12 | rwNormal read/write | 0x0 | Number of Failures: Specifies the number of failures after which the execution of commands and the capture of read data should stop if SONF bit of this register is set. Execution of commands and the capture of read data will stop after (NFAIL+1) failures if SONF is set. |
| EADDR | 11:8 | rwNormal read/write | 0x0 | End Address: Cache word address where the execution of command should end. |
| SADDR | 7:4 | rwNormal read/write | 0x0 | Start Address: Cache word address where the execution of commands should begin. |
| DINST | 3:0 | rwNormal read/write | 0x0 | DCU Instruction: Selects the DCU command to be executed: Valid values are: 0000 = NOP: No operation 0001 = Run: Triggers the execution of commands in the command cache. 0010 = Stop: Stops the execution of commands in the command cache. 0011 = Stop Loop: Stops the execution of an infinite loop in the command cache. 0100 = Reset: Resets all DCU run time registers. See Section for details. 0101 - 1111 RESERVED Note: Controller/software must ensure that all DRAM timings have been met for all prior issued commands before triggering any PUB Mode operation. |