DCUSR0 (DDR_PHY) Register Description
| Register Name | DCUSR0 |
|---|---|
| Offset Address | 0x0000000318 |
| Absolute Address | 0x00FD080318 (DDR_PHY) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | DCU Status Register 0 |
DCUSR0 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:3 | roRead-only | 0x0 | Reserved. Return zeros on reads. |
| CFULL | 2 | roRead-only | 0x0 | Capture Full: Indicates if set that the capture cache is full. |
| CFAIL | 1 | roRead-only | 0x0 | Capture Fail: Indicates if set that that at least one read data word has failed. |
| RDONE | 0 | roRead-only | 0x0 | Run Done: Indicates if set that the DCU has finished executing the commands in the command cache. This bit is also set to indicate that a STOP command has successfully been executed and command execution has stopped. |