DDRC_EXT_REFRESH (DDR_QOS_CTRL) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DDRC_EXT_REFRESH (DDR_QOS_CTRL) Register Description

Register NameDDRC_EXT_REFRESH
Offset Address0x0000000020
Absolute Address 0x00FD090020 (DDR_QOS_CTRL)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionDDRC External Refresh Control Register

DDRC_EXT_REFRESH (DDR_QOS_CTRL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:1razRead as zero0x0Reserved for future use
ENABLE 0rwNormal read/write0x0Enable DDRC External refresh control through QoS Controller