DDRC_MRR_DATA1 (DDR_QOS_CTRL) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DDRC_MRR_DATA1 (DDR_QOS_CTRL) Register Description

Register NameDDRC_MRR_DATA1
Offset Address0x0000000520
Absolute Address 0x00FD090520 (DDR_QOS_CTRL)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionDDRC MRR Register Data

DDRC_MRR_DATA1 (DDR_QOS_CTRL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
MSB31:0roRead-only0x0DDRC MRR Register MSB Data