DDRC_MRR_STATUS (DDR_QOS_CTRL) Register Description
| Register Name | DDRC_MRR_STATUS |
|---|---|
| Offset Address | 0x0000000518 |
| Absolute Address | 0x00FD090518 (DDR_QOS_CTRL) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | DDRC MRR Register Status |
DDRC_MRR_STATUS (DDR_QOS_CTRL) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:4 | razRead as zero | 0x0 | Reserved for future use |
| VALID_CNT | 3:1 | roRead-only | 0x0 | Indicate How many valid data available in FIFO. |
| VALID | 0 | roRead-only | 0x0 | Indicate Valid data is available in FIFO. |