DDR_CLK_CTRL (DDR_QOS_CTRL) Register Description
| Register Name | DDR_CLK_CTRL |
|---|---|
| Offset Address | 0x0000000700 |
| Absolute Address | 0x00FD090700 (DDR_QOS_CTRL) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000001 |
| Description | DDR Sub system clock control |
DDR_CLK_CTRL (DDR_QOS_CTRL) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:2 | razRead as zero | 0x0 | Reserved for future use |
| CLKACT | 0 | rwNormal read/write | 0x1 | Clock active signal. Switch to 0 to disable the clock |