DDR_CTRL (CRF_APB) Register Description
| Register Name | DDR_CTRL |
|---|---|
| Offset Address | 0x0000000080 |
| Absolute Address | 0x00FD1A0080 (CRF_APB) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000500 |
| Description | DDR Memory Controller Clock Generator Control. |
DDR_CTRL (CRF_APB) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| DIVISOR0 | 13:8 | rwNormal read/write | 0x5 | 6-bit divider. |
| SRCSEL | 2:0 | rwNormal read/write | 0x0 | Clock generator input source. 000: DPLL 001: VPLL |