DDR_QOS_CTRL Module

Zynq UltraScale+ Devices Register Reference (UG1087)
Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DDR_QOS_CTRL Module Description

Module NameDDR_QOS_CTRL Module
Modules of this TypeDDR_QOS_CTRL
Base Addresses 0x00FD090000 (DDR_QOS_CTRL)
DescriptionDDR Quality of Service (QoS)

DDR_QOS_CTRL Module Register Summary

Register NameOffset AddressWidthTypeReset ValueDescription
PORT_TYPE0x000000000032mixedMixed types. See bit-field details.0x0000A845Set Port Type Register
QOS_CTRL0x000000000432mixedMixed types. See bit-field details.0x00400000Set Port Type Register
RD_HPR_THRSLD0x000000000832mixedMixed types. See bit-field details.0x00000000Set Value for Read HPR (High Priority Read) CAM Threshold
RD_LPR_THRSLD0x000000000C32mixedMixed types. See bit-field details.0x00000000Set Value for Read LPR (Low Priority Read) CAM Threshold
WR_THRSLD0x000000001032mixedMixed types. See bit-field details.0x00000000Set Value for Write CAM Threshold
ZQCS_CTRL00x000000001432mixedMixed types. See bit-field details.0x00000000ZQCS Control Register 0
ZQCS_CTRL10x000000001832mixedMixed types. See bit-field details.0x00000000ZQCS Control Register 2
ZQCS_STATUS0x000000001C32mixedMixed types. See bit-field details.0x00000000ZQCS Status Register
DDRC_EXT_REFRESH0x000000002032mixedMixed types. See bit-field details.0x00000000DDRC External Refresh Control Register
QOS_IRQ_STATUS0x000000020032mixedMixed types. See bit-field details.0x00000000Interrupt Status Register for intrN. This is a sticky register that holds the value of the interrupt until cleared by a value of 1.
QOS_IRQ_MASK0x000000020432mixedMixed types. See bit-field details.0x000007FFInterrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER.
QOS_IRQ_ENABLE0x000000020832mixedMixed types. See bit-field details.0x00000000Interrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0)
QOS_IRQ_DISABLE0x000000020C32mixedMixed types. See bit-field details.0x00000000Interrupt Disable Register. A write of one to this location will mask the interrupt. (IMR: 1)
DDRC_URGENT0x000000051032mixedMixed types. See bit-field details.0x00000000DDRC URGENT Sideband signal control register
DDRC_QVN_CTRL0x000000051432mixedMixed types. See bit-field details.0x0000003CDDRC QVN Control register
DDRC_MRR_STATUS0x000000051832mixedMixed types. See bit-field details.0x00000000DDRC MRR Register Status
DDRC_MRR_DATA00x000000051C32roRead-only0x00000000DDRC MRR Register Data
DDRC_MRR_DATA10x000000052032roRead-only0x00000000DDRC MRR Register Data
DDRC_MRR_DATA20x000000052432mixedMixed types. See bit-field details.0x00000000DDRC MRR Register Data
DDRC_MRR_DATA30x000000052832roRead-only0x00000000DDRC MRR Register Data
DDRC_MRR_DATA40x000000052C32roRead-only0x00000000DDRC MRR Register Data
DDRC_MRR_DATA50x000000053032mixedMixed types. See bit-field details.0x00000000DDRC MRR Register Data
DDRC_MRR_DATA60x000000053432roRead-only0x00000000DDRC MRR Register Data
DDRC_MRR_DATA70x000000053832roRead-only0x00000000DDRC MRR Register Data
DDRC_MRR_DATA80x000000053C32mixedMixed types. See bit-field details.0x00000000DDRC MRR Register Data
DDRC_MRR_DATA90x000000054032roRead-only0x00000000DDRC MRR Register Data
DDRC_MRR_DATA100x000000054432roRead-only0x00000000DDRC MRR Register Data
DDRC_MRR_DATA110x000000054832mixedMixed types. See bit-field details.0x00000000DDRC MRR Register Data
DDR_CLK_CTRL0x000000070032mixedMixed types. See bit-field details.0x00000001DDR Sub system clock control
DDRC_VPR_COLLISION0x000000080032rwNormal read/write0x00000000ECO Register