DERATEEN (DDRC) Register Description
| Register Name | DERATEEN |
|---|---|
| Offset Address | 0x0000000020 |
| Absolute Address | 0x00FD070020 (DDRC) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Temperature Derate Enable Register |
All register fields are static, unless described otherwise in the register field description. Static registers can only be written when the controller is in reset.
DERATEEN (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| rc_derate_value | 9:8 | rwNormal read/write | 0x0 | Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating uses +2. - 2 - Derating uses +3. - 3 - Derating uses +4. The required number of cycles for derating can be determined by dividing 3.75ns by the core_ddrc_core_clk period, and rounding up the next integer. |
| derate_byte | 7:4 | rwNormal read/write | 0x0 | Derate byte Indicates which byte of the MRR data is used for derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. |
| derate_value | 1 | rwNormal read/write | 0x0 | Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Can be 0 or 1 for LPDDR3/LPDDR4, depending if +1.875 ns is less than a core_ddrc_core_clk period or not. |
| derate_enable | 0 | rwNormal read/write | 0x0 | Enables derating - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value. This field must be set to 0 for non-LPDDR3/LPDDR4 mode. Programming Mode: Dynamic |