DERATEINT_SHADOW (DDRC) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DERATEINT_SHADOW (DDRC) Register Description

Register NameDERATEINT_SHADOW
Offset Address0x0000002024
Absolute Address 0x00FD072024 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x00800000
DescriptionTemperature Derate Interval Shadow Register

This register is static. Static registers can only be written when the controller is in reset.

DERATEINT_SHADOW (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
mr4_read_interval31:0rwNormal read/write0x800000LPDDR3/LPDDR4: Interval between two MR4 reads, used to derate the timing parameters.
This register must not be set to zero