DEVAFF0 (A53_PMU_2) Register Description
| Register Name | DEVAFF0 |
|---|---|
| Offset Address | 0x0000000FA8 |
| Absolute Address | 0x00FEE30FA8 (CORESIGHT_A53_PMU_2) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x80000002 |
| Description | Performance Monitors Device Affinity Register 0 |
DEVAFF0 (A53_PMU_2) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| PMDEVAFF0 | 31:0 | roRead-only | 0x80000002 | MPIDR_EL1 low half. Read-only copy of the low half of MPIDR_EL1, as seen from the highest implemented exception level. |