DEVARCH (A53_ETM_2) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DEVARCH (A53_ETM_2) Register Description

Register NameDEVARCH
Offset Address0x0000000FBC
Absolute Address 0x00FEE40FBC (CORESIGHT_A53_ETM_2)
Width32
TyperoRead-only
Reset Value0x47704A13
DescriptionDevice Architecture Register

DEVARCH (A53_ETM_2) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ARCHITECT31:21roRead-only0x23BDefines the architecture of the component. For trace, this is Arm Limited.Bits [31:28] are the JEP 106 continuation code, 0x4.Bits [27:21] are the JEP 106 ID code, 0x3B.
PRESENT20roRead-only0x1When set to 1, indicates that the DEVARCH is present.This field is RAO.
REVISION19:16roRead-only0x0Defines the architecture revision. For architectures defined by Arm this is the minor revision.For trace, the revision defined by ETMv4 is 0x0.All other values are reserved.
ARCHID15:0roRead-only0x4A13Defines this part to be a v8-A debug component. For architectures defined by Arm this is further subdivided.For trace, bits [15:12] are the architecture version, 0x4; bits [11:0] are the architecture part number, 0xA13.This corresponds to trace architecture version ETMv4.