DEVARCH (A53_PMU_3) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DEVARCH (A53_PMU_3) Register Description

Register NameDEVARCH
Offset Address0x0000000FBC
Absolute Address 0x00FEF30FBC (CORESIGHT_A53_PMU_3)
Width32
TyperoRead-only
Reset Value0x47702A16
DescriptionPerformance Monitors Device Architecture Register

DEVARCH (A53_PMU_3) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ARCHITECT31:21roRead-only0x23BDefines the architecture of the component. For Performance Monitors, this is Arm Limited.Bits [31:28] are the JEP 106 continuation code, 0x4.Bits [27:21] are the JEP 106 ID code, 0x3B.
PRESENT20roRead-only0x1When set to 1, indicates that the DEVARCH is present.This field is 1 in v8-A.
REVISION19:16roRead-only0x0Defines the architecture revision. For architectures defined by Arm this is the minor revision.For Performance Monitors, the revision defined by v8-A is 0x0.All other values are reserved.
ARCHID15:0roRead-only0x2A16Defines this part to be a v8-A debug component. For architectures defined by Arm this is further subdivided.For Performance Monitors:Bits [15:12] are the architecture version, 0x2.Bits [11:0] are the architecture part number, 0xA16.This corresponds to Performance Monitors architecture version PMUv3.