DEVARCH (STM) Register Description
Register Name | DEVARCH |
---|---|
Offset Address | 0x0000000FBC |
Absolute Address | 0x00FE9C0FBC (CORESIGHT_SOC_STM) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | Indicates the architect and architecture of the STM. For the STM-500, the architect is Arm, and the architecture is STMv1.1 |
DEVARCH (STM) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
ARCHITECT | 31:21 | roRead-only | 0x0 | Defines the architect of the component. Bits[31:28] indicate the DEP106 continuation code of the architect. Bits[27:21] indicate the JEP106 identification code of the architect. See the Standard Manufacturers Identification Code for information about JEP106: 23Bh: Arm |
PRESENT | 20 | roRead-only | 0x0 | Indicates the presence of the STMDEVARCH register: 1: present. |
REVISION | 19:16 | roRead-only | 0x0 | Architecture revision. Returns the revision of the architecture that the ARCHID field specifies. For the STM-500, this value is 1h, indicating the STMv1.1 architecture. |
ARCHID | 14:0 | roRead-only | 0x0 | Architecture ID. Returns a value that identifies the architecture of the component. For the STM-500, this value is 15h0A63, indicating the STMv1 architecture. |