DEVARCH (STM) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DEVARCH (STM) Register Description

Register NameDEVARCH
Offset Address0x0000000FBC
Absolute Address 0x00FE9C0FBC (CORESIGHT_SOC_STM)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionIndicates the architect and architecture of the STM. For the STM-500, the architect is Arm, and the architecture is STMv1.1

DEVARCH (STM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ARCHITECT31:21roRead-only0x0Defines the architect of the component. Bits[31:28] indicate the DEP106 continuation code of the architect. Bits[27:21] indicate the JEP106 identification code of the architect. See the Standard Manufacturers Identification Code for information about JEP106:
23Bh: Arm
PRESENT20roRead-only0x0Indicates the presence of the STMDEVARCH register:
1: present.
REVISION19:16roRead-only0x0Architecture revision. Returns the revision of the architecture that the ARCHID field specifies. For the STM-500, this value is 1h, indicating the STMv1.1 architecture.
ARCHID14:0roRead-only0x0Architecture ID. Returns a value that identifies the architecture of the component. For the STM-500, this value is 15h0A63, indicating the STMv1 architecture.