DEVID (ETR) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DEVID (ETR) Register Description

Register NameDEVID
Offset Address0x0000000FC8
Absolute Address 0x00FE970FC8 (CORESIGHT_SOC_ETR)
Width32
TyperoRead-only
Reset Value0x00001A40
DescriptionThis register indicates the capabilities of the CoreSight TMC.

DEVID (ETR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
WBUF_DEPTH13:11roRead-only0x3Indicates the number of entries in the Write buffer is 8
MEMWIDTH10:8roRead-only0x2Indicates the width of the Memory interfaceis 32 bits
CONFIGTYPE 7:6roRead-only0x1Indicates configured as ETR
CLKSCHEME 5roRead-only0x0Indicates TMC RAM synchronous to CLK
ATBINPORTCOUNT 4:0roRead-only0x0Indicates no multiplexing