DFILPCFG1 (DDRC) Register Description
| Register Name | DFILPCFG1 |
|---|---|
| Offset Address | 0x000000019C |
| Absolute Address | 0x00FD07019C (DDRC) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | DFI Low Power Configuration Register 1 |
This register is static. Static registers can only be written when the controller is in reset.
DFILPCFG1 (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| dfi_lp_wakeup_mpsm | 7:4 | rwNormal read/write | 0x0 | DDR4: Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFIs tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited |
| dfi_lp_en_mpsm | 0 | rwNormal read/write | 0x0 | DDR4: Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit. - 0 - Disabled - 1 - Enabled |