DFIMISC (DDRC) Register Description
| Register Name | DFIMISC |
|---|---|
| Offset Address | 0x00000001B0 |
| Absolute Address | 0x00FD0701B0 (DDRC) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000001 |
| Description | DFI Miscellaneous Control Register |
All register fields are static, unless described otherwise in the register field description. Static registers can only be written when the controller is in reset.
DFIMISC (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| dfi_data_cs_polarity | 2 | rwNormal read/write | 0x0 | Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signals are active low - 1: Signals are active high |
| phy_dbi_mode | 1 | rwNormal read/write | 0x0 | DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. - 1 - PHY implements DBI functionality. |
| dfi_init_complete_en | 0 | rwNormal read/write | 0x1 | PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialization Programming Mode: Quasi-dynamic Group 3 |