DFITMG0 (DDRC) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DFITMG0 (DDRC) Register Description

Register NameDFITMG0
Offset Address0x0000000190
Absolute Address 0x00FD070190 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x07020002
DescriptionDFI Timing Register 0

All register fields are static, unless described otherwise in the register field description. Static registers can only be written when the controller is in reset.

DFITMG0 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
dfi_t_ctrl_delay28:24rwNormal read/write0x7Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to increment this parameter by RDIMMs extra cycle of latency in terms of DFI clock.
This should be set to 4.
Programming Mode: Quasi-dynamic Group 4
dfi_rddata_use_sdr23rwNormal read/write0x0Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values
Selects whether value in DFITMG0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles:
- 0 in terms of HDR clock cycles
- 1 in terms of SDR clock cycles
This should be set to 1.
dfi_t_rddata_en21:16rwNormal read/write0x2Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal.
For DDR3 and DDR4, set to RL-4.
For LPDDR3, set to RL+int(1.5/clock_period)-4.
For LPDDR4 with speed bin >= 1600, set to RL+int(1.5/clock_period)-4.
For LPDDR4 with speed bin < 1600, set to RL-3.
This corresponds to the DFI parameter trddata_en.
Unit: Clocks
Programming Mode: Quasi-dynamic Group 1 and Group 4
dfi_wrdata_use_sdr15rwNormal read/write0x0Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values
Selects whether value in DFITMG0.dfi_tphy_wrlat
is in terms of SDR or HDR clock cycles
Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or HDR clock cycles
- 0 in terms of HDR clock cycles
- 1 in terms of SDR clock cycles
This should be set to 1.
dfi_tphy_wrdata13:8rwNormal read/write0x0Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal.
This corresponds to the DFI timing parameter tphy_wrdata. This should be set to 2. Note, max supported value is 8.
Unit: Clocks
Programming Mode: Quasi-dynamic Group 4
dfi_tphy_wrlat 5:0rwNormal read/write0x2Write latency
Number of clocks from the write command to write data enable (dfi_wrdata_en).
This corresponds to the DFI timing parameter tphy_wrlat.
This should be set to WL-3 for DDR3 and DDR4 component and SODIMM designs.
It should be set to WL-2 for LPDDR3 and LPDDR4 designs as well as DDR3 and DDR4 RDIMM designs.
Programming Mode: Quasi-dynamic Group 1 and Group 4