DFITMG1 (DDRC) Register Description
| Register Name | DFITMG1 |
|---|---|
| Offset Address | 0x0000000194 |
| Absolute Address | 0x00FD070194 (DDRC) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000404 |
| Description | DFI Timing Register 1 |
All register fields are quasi-dynamic group 4, unless described otherwise in the register field description. Group 4 registers can be written depending on MSTR.frequency_mode.
DFITMG1 (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| dfi_t_cmd_lat | 31:28 | rwNormal read/write | 0x0 | Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated command is driven. This field is used for CAL mode, should be set to 0 or the value which matches the CAL mode register setting in the DRAM. If the PHY can add the latency for CAL mode, this should be set to 0. Valid Range: 0, 3, 4, 5, 6, and 8 Programming Mode: Quasi-dynamic Group 2 and Group 4 |
| dfi_t_parin_lat | 25:24 | rwNormal read/write | 0x0 | Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven. |
| dfi_t_wrdata_delay | 20:16 | rwNormal read/write | 0x0 | Specifies the number of DFI clocks between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. Set to twrdata_delay, a new timing parameter introduced in DFI 3.0. Value to be programmed is in terms of DFI clocks, not PHY clocks. Divide PHYs value by 2 and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. For DDR4 and LPDDR4, this should be set to 3. For DDR3 and LPDDR3, this should be set to 2. Unit: Clocks |
| dfi_t_dram_clk_disable | 11:8 | rwNormal read/write | 0x4 | Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. |
| dfi_t_dram_clk_enable | 3:0 | rwNormal read/write | 0x4 | Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. |