DFITMG2 (DDRC) Register Description
| Register Name | DFITMG2 |
|---|---|
| Offset Address | 0x00000001B4 |
| Absolute Address | 0x00FD0701B4 (DDRC) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000202 |
| Description | DFI Timing Register 2 |
This register is quasi-dynamic group 2 and group 4. Group 2 registers can be written in self-refresh, deep power-down, and maximum power saving modes. Group 4 registers can be written depending on MSTR.frequency_mode.
DFITMG2 (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| dfi_tphy_rdcslat | 13:8 | rwNormal read/write | 0x2 | >Number of clocks between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. This should be set to dfi_t_rddata_en - 2. |
| dfi_tphy_wrcslat | 5:0 | rwNormal read/write | 0x2 | Number of clocks between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. For non-RDIMM systems, this should be set to dfi_tphy_wrlat-5. For RDIMM systems, this should be set to 2. |