DFIUPD0 (DDRC) Register Description
| Register Name | DFIUPD0 |
|---|---|
| Offset Address | 0x00000001A0 |
| Absolute Address | 0x00FD0701A0 (DDRC) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00400003 |
| Description | DFI Update Register 0 |
All register fields are static, unless described otherwise in the register field description. Static registers can only be written when the controller is in reset.
DFIUPD0 (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| dis_auto_ctrlupd | 31 | rwNormal read/write | 0x0 | When 1, disable the automatic dfi_ctrlupd_req generation by the DDRC. The core must issue the dfi_ctrlupd_req signal using register reg_ddrc_ctrlupd. When 0, DDRC issues dfi_ctrlupd_req periodically. Quasi-dynamic Group 2 |
| dis_auto_ctrlupd_srx | 30 | rwNormal read/write | 0x0 | When 1, disable the automatic dfi_ctrlupd_req generation by the DDRC following a self-refresh exit. The core must issue the dfi_ctrlupd_req signal using register reg_ddrc_ctrlupd. When 0, DDRC issues a dfi_ctrlupd_req after exiting self-refresh. |
| dfi_t_ctrlup_max | 25:16 | rwNormal read/write | 0x40 | Specifies the maximum number of clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. Unit: Clocks |
| dfi_t_ctrlup_min | 9:0 | rwNormal read/write | 0x3 | Specifies the minimum number of clock cycles that the dfi_ctrlupd_req signal must be asserted. The DDRC expects the PHY to respond within this time. If the PHY does not respond, the DDRC will de-assert dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. Unit: Clocks |