DIDR (R5_DBG_0) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DIDR (R5_DBG_0) Register Description

Register NameDIDR
Offset Address0x0000000000
Absolute Address 0x00FEBF0000 (CORESIGHT_R5_DBG_0)
Width32
TyperoRead-only
Reset Value0x77140013
DescriptionDebug ID register

DIDR (R5_DBG_0) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
WRP31:28roRead-only0x7Number of Watchpoint Register Pairs:
0111 = 8 WRPs
BRP27:24roRead-only0x7Number of Breakpoint Register Pairs:
0111 = 8 BRPs
Context23:20roRead-only0x1Number of Breakpoint Register Pairs (BRP) with context ID comparison capability:
0001 = 2 BRPs have context IDcomparison capability
Arch_Ver19:16roRead-only0x4Debug architecture version:
0100 denotes Armv7 Debug
DEVID_imp15roRead-only0x0Indicates whether DEVID is implemented.
0x0 = not implemented
Variant 7:4roRead-only0x1Implementation-defined variant number. This is the major revision number n in the rn part of the rnpn description of the product revision status.
Revision 3:0roRead-only0x3Implementation-defined revisionnumber. This is the minor revision number n in the pn part of the rnpn description of the product revision status.