DISPLAY_PORT Module Description
| Module Name | DISPLAY_PORT Module |
|---|---|
| Modules of this Type | DISPLAY_PORT |
| Base Addresses | 0x00FD4A0000 (DISPLAY_PORT) |
| Description | DisplayPort Controller |
DISPLAY_PORT Module Register Summary
| Register Name | Offset Address | Width | Type | Reset Value | Description |
|---|---|---|---|---|---|
| DP_LINK_BW_SET | 0x0000000000 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Sets the value of the main link bandwidth for the sink device. |
| DP_LANE_COUNT_SET | 0x0000000004 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | To set the lane count |
| DP_ENHANCED_FRAME_EN | 0x0000000008 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | To enable enhanced framing |
| DP_TRAINING_PATTERN_SET | 0x000000000C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | To force training pattern |
| DP_LINK_QUAL_PATTERN_SET | 0x0000000010 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | To transmit the link quality pattern |
| DP_SCRAMBLING_DISABLE | 0x0000000014 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | DP_SCRAMBLING_DISABLE |
| DP_DOWNSPREAD_CTRL | 0x0000000018 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | For down-spreading control |
| DP_SOFTWARE_RESET | 0x000000001C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Soft reset of DP Core |
| DP_COMP_PATTERN_80BIT_1 | 0x0000000020 | 32 | rwNormal read/write | 0x00000000 | 32 bits of 80-bit custom pattern that is used for LINK quality test. These bits are valid when Bit 2 of DP_LINK_QUAL_PATTERN_SET 0x10 register is set to 1 |
| DP_COMP_PATTERN_80BIT_2 | 0x0000000024 | 32 | rwNormal read/write | 0x00000000 | Description same as DP_COMP_PATTERN_80BIT_1 (0x20) |
| DP_COMP_PATTERN_80BIT_3 | 0x0000000028 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Description same as DP_COMP_PATTERN_80BIT_1 (0x20) |
| DP_TRANSMITTER_ENABLE | 0x0000000080 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Enable the basic operations of the transmitter. |
| DP_MAIN_STREAM_ENABLE | 0x0000000084 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Enable the transmission of main link video information. |
| DP_FORCE_SCRAMBLER_RESET | 0x00000000C0 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Reads from this register always return 0x0. |
| DP_VERSION_REGISTER | 0x00000000F8 | 32 | roRead-only | 0x04010000 | Core version register |
| DP_CORE_ID | 0x00000000FC | 32 | roRead-only | 0x01020000 | Returns the unique identification code of the core and the current revision level |
| DP_AUX_COMMAND_REGISTER | 0x0000000100 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | DP_AUX_COMMAND_REGISTER |
| DP_AUX_WRITE_FIFO | 0x0000000104 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | . FIFO containing up to 16 bytes of write data for the current AUX channel command |
| DP_AUX_ADDRESS | 0x0000000108 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Specifies the address for the current AUX channel command. |
| DP_AUX_CLOCK_DIVIDER | 0x000000010C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | . Contains the clock divider value for generating the internal 1MHz clock from the APB host interface clock. The clock divider register provides integer division only and does not support fractional APB clock rates (for example, set to 75 for a 75 MHz APB clock). |
| DP_TX_USER_FIFO_OVERFLOW | 0x0000000110 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | . Indicates an overflow in the user FIFO. The event may occur if the video rate does not match the TU size programming. |
| DP_INTERRUPT_SIGNAL_STATE | 0x0000000130 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Contains the raw signal values for those conditions which may cause an interrupt. |
| DP_AUX_REPLY_DATA | 0x0000000134 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Maps to the internal FIFO which contains up to 16 bytes of information received during the AUX channel reply. Reply data is read from the FIFO starting with byte 0. The number of bytes in the FIFO corresponds to the number of bytes requested. |
| DP_AUX_REPLY_CODE | 0x0000000138 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Reply code received from the most recent AUX Channel request. The AUX Reply Code corresponds to the code from the DisplayPort specification |
| DP_AUX_REPLY_COUNT | 0x000000013C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Provides an internal counter of the number of AUX reply transactions received on the AUX Channel. Writing to this register clears the count. |
| DP_REPLY_DATA_COUNT | 0x0000000148 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Returns the total number of data bytes actually received during a transaction. This register does not use the length byte of the transaction header. |
| DP_REPLY_STATUS | 0x000000014C | 32 | mixedMixed types. See bit-field details. | 0x00000010 | DP_REPLY_STATUS |
| DP_HPD_DURATION | 0x0000000150 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | DP_HPD_DURATION |
| DP_MAIN_STREAM_HTOTAL | 0x0000000180 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Specifies the total number of clocks in the horizontal framing period for the main stream video signal. |
| DP_MAIN_STREAM_VTOTAL | 0x0000000184 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Provides the total number of lines in the main stream video frame |
| DP_MAIN_STREAM_HSWIDTH | 0x000000018C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Sets the width of the horizontal sync pulse. |
| DP_MAIN_STREAM_VSWIDTH | 0x0000000190 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Sets the width of the vertical sync pulse. |
| DP_MAIN_STREAM_HRES | 0x0000000194 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Horizontal resolution of the main stream video source |
| DP_MAIN_STREAM_VRES | 0x0000000198 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Vertical resolution of the main stream video source |
| DP_MAIN_STREAM_HSTART | 0x000000019C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Number of clocks between the leading edge of the horizontal sync and the start of active data |
| DP_MAIN_STREAM_VSTART | 0x00000001A0 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Number of lines between the leading edge of the vertical sync and the first line of active data. |
| DP_MAIN_STREAM_MISC0 | 0x00000001A4 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Miscellaneous stream attributes.Implements the attribute information contained in the DisplayPort MISC0 register described in section 2.2.4 of the standard. |
| DP_MAIN_STREAM_MISC1 | 0x00000001A8 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | MAIN_STREAM_MISC1. Miscellaneous stream attributes.Implements the attribute information contained in the DisplayPort MISC1 register described in section 2.2.4 of the standard. |
| DP_MAIN_STREAM_M_VID | 0x00000001AC | 32 | mixedMixed types. See bit-field details. | 0x00000000 | M value for the video stream as computed by the source core. If synchronous clocking mode is used, this register must be written with the M value. |
| DP_MSA_TRANSFER_UNIT_SIZE | 0x00000001B0 | 32 | mixedMixed types. See bit-field details. | 0x00000040 | Sets the size of a transfer unit in the framing logic On reset, transfer size is set to 64. |
| DP_MAIN_STREAM_N_VID | 0x00000001B4 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | N value for the video stream as computed by the source core. If synchronous clocking mode is used, this register must be written with the N value. |
| DP_USER_PIX_WIDTH | 0x00000001B8 | 32 | mixedMixed types. See bit-field details. | 0x00000001 | User pixel width size |
| DP_USER_DATA_COUNT_PER_LANE | 0x00000001BC | 32 | mixedMixed types. See bit-field details. | 0x00000000 | This register is used to translate the number of pixels per line to the native internal 16-bit datapath. |
| DP_MIN_BYTES_PER_TU | 0x00000001C4 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Programs source to use MIN number of bytes per transfer unit. The calculation should be done based on the DisplayPort specification. |
| DP_FRAC_BYTES_PER_TU | 0x00000001C8 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Calculating MIN bytes per TU will often not be a whole number.This register is used to hold the fractional component |
| DP_INIT_WAIT | 0x00000001CC | 32 | mixedMixed types. See bit-field details. | 0x00000020 | This register defines the number of initial wait cycles at the start of a new line by the Framing logic. This allows enough data to be buffered in the input FIFO. |
| DP_PHY_RESET | 0x0000000200 | 32 | mixedMixed types. See bit-field details. | 0x00010002 | Reset the transmitter PHY. |
| DP_TRANSMIT_PRBS7 | 0x0000000230 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Enable the pseudo random bit sequence 7 pattern transmission for link quality assessment. PRBS is generated by the DP transmit controller only. PRBS feature of Cadence GT is unused |
| DP_PHY_CLOCK_SELECT | 0x0000000234 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Instructs the PHY PLL to generate the proper clock frequency for the required link rate |
| DP_TX_PHY_POWER_DOWN | 0x0000000238 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Control PHY Power down |
| DP_PHY_PRECURSOR_LANE_0 | 0x000000024C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Set the pre-cursor level(post cursor 1for cadence GT) for lane 0 of the DisplayPort link |
| DP_PHY_PRECURSOR_LANE_1 | 0x0000000250 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Set the pre-cursor level(post cursor 1 for Cadence GT) for lane 1 of the DisplayPort link |
| DP_PHY_STATUS | 0x0000000280 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Provides the current status from the PHY. |
| DP_TX_AUDIO_CONTROL | 0x0000000300 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Enables audio stream packets in main link and provides buffer control. |
| DP_TX_AUDIO_CHANNELS | 0x0000000304 | 32 | rwNormal read/write | 0x00000000 | TX_AUDIO_CHANNELS. Used to input active channel count. Transmitter collects audio samples based on this information. |
| DP_TX_AUDIO_INFO_DATA0 | 0x0000000308 | 32 | woWrite-only | 0x00000000 | Word formatted as per CEA 861-C Info Frame. |
| DP_TX_AUDIO_INFO_DATA1 | 0x000000030C | 32 | woWrite-only | 0x00000000 | Word formatted as per CEA 861-C Info Frame. |
| DP_TX_AUDIO_INFO_DATA2 | 0x0000000310 | 32 | woWrite-only | 0x00000000 | Word formatted as per CEA 861-C Info Frame. |
| DP_TX_AUDIO_INFO_DATA3 | 0x0000000314 | 32 | woWrite-only | 0x00000000 | Word formatted as per CEA 861-C Info Frame. |
| DP_TX_AUDIO_INFO_DATA4 | 0x0000000318 | 32 | woWrite-only | 0x00000000 | Word formatted as per CEA 861-C Info Frame. |
| DP_TX_AUDIO_INFO_DATA5 | 0x000000031C | 32 | woWrite-only | 0x00000000 | Word formatted as per CEA 861-C Info Frame. |
| DP_TX_AUDIO_INFO_DATA6 | 0x0000000320 | 32 | woWrite-only | 0x00000000 | Word formatted as per CEA 861-C Info Frame. |
| DP_TX_AUDIO_INFO_DATA7 | 0x0000000324 | 32 | woWrite-only | 0x00000000 | Word formatted as per CEA 861-C Info Frame. |
| DP_TX_M_AUD | 0x0000000328 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | M value of audio stream as computed by transmitter |
| DP_TX_N_AUD | 0x000000032C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | TX_AUDIO_NAUD. N value of audio stream as computed by transmitter. |
| DP_TX_AUDIO_EXT_DATA0 | 0x0000000330 | 32 | woWrite-only | 0x00000000 | Word formatted as per Extension packet described in protocol specification. Extended packet is fixed to 32 Bytes length. The controller has buffer space for only one extended packet. |
| DP_TX_AUDIO_EXT_DATA1 | 0x0000000334 | 32 | woWrite-only | 0x00000000 | 2nd word of the 9 words of the extended packet |
| DP_TX_AUDIO_EXT_DATA2 | 0x0000000338 | 32 | woWrite-only | 0x00000000 | 3rd word of the 9 words of the extended packet |
| DP_TX_AUDIO_EXT_DATA3 | 0x000000033C | 32 | woWrite-only | 0x00000000 | 4th word of the 9 words of the extended packet |
| DP_TX_AUDIO_EXT_DATA4 | 0x0000000340 | 32 | woWrite-only | 0x00000000 | 5th word of the 9 words of the extended packet |
| DP_TX_AUDIO_EXT_DATA5 | 0x0000000344 | 32 | woWrite-only | 0x00000000 | 6th word of the 9 words of the extended packet |
| DP_TX_AUDIO_EXT_DATA6 | 0x0000000348 | 32 | woWrite-only | 0x00000000 | 7th word of the 9 words of the extended packet |
| DP_TX_AUDIO_EXT_DATA7 | 0x000000034C | 32 | woWrite-only | 0x00000000 | 8th word of the 9 words of the extended packet |
| DP_TX_AUDIO_EXT_DATA8 | 0x0000000350 | 32 | woWrite-only | 0x00000000 | 9th word of the 9 words of the extended packet |
| DP_INT_STATUS | 0x00000003A0 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Interrupt Status Register for intrN. This is a sticky register that holds the value of the interrupt until cleared by a value of 1. |
| DP_INT_MASK | 0x00000003A4 | 32 | mixedMixed types. See bit-field details. | 0xFFFFF03F | Interrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER. |
| DP_INT_EN | 0x00000003A8 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Interrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0) |
| DP_INT_DS | 0x00000003AC | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Interrupt Disable Register. A write of one to this location will mask the interrupt. (IMR: 1) |
| V_BLEND_BG_CLR_0 | 0x000000A000 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_BG_CLR_0: Sets background color of the layers |
| V_BLEND_BG_CLR_1 | 0x000000A004 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_BG_CLR_1: Sets background color of the layers |
| V_BLEND_BG_CLR_2 | 0x000000A008 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_BG_CLR_2: Sets background color of the layers. |
| V_BLEND_SET_GLOBAL_ALPHA_REG | 0x000000A00C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | To set the global alpha |
| V_BLEND_OUTPUT_VID_FORMAT | 0x000000A014 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_OUTPUT_VID_FORMAT: |
| V_BLEND_LAYER0_CONTROL | 0x000000A018 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_LAYER0_CONTROL: Layer 0 is always video pixel |
| V_BLEND_LAYER1_CONTROL | 0x000000A01C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_LAYER1_CONTROL: Layer 1 is always Graphcis |
| V_BLEND_RGB2YCBCR_COEFF0 | 0x000000A020 | 32 | mixedMixed types. See bit-field details. | 0x00001000 | V_BLEND_RGB2YCBCR_COEFF0:Coefficient values from Matrix for output color space convertor. A total of 9 values are needed to form 3x3 matrix. The value is scaled by 2^12 and stored in 15-bit signed format.(1bit reserved). 12Bits out of the 15 represent fractional value and 2 bits for decimal value and one signed bit. The order of programming values is from v0 - v8 |
| V_BLEND_RGB2YCBCR_COEFF1 | 0x000000A024 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_RGB2YCBCR_COEFF1:Description same as V_BLEND_RGB2YCBCR_COEFF0 |
| V_BLEND_RGB2YCBCR_COEFF2 | 0x000000A028 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_RGB2YCBCR_COEFF2:Description same as V_BLEND_RGB2YCBCR_COEFF0 |
| V_BLEND_RGB2YCBCR_COEFF3 | 0x000000A02C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_RGB2YCBCR_COEFF3:Description same as V_BLEND_RGB2YCBCR_COEFF0 |
| V_BLEND_RGB2YCBCR_COEFF4 | 0x000000A030 | 32 | mixedMixed types. See bit-field details. | 0x00001000 | V_BLEND_RGB2YCBCR_COEFF4:Description same as V_BLEND_RGB2YCBCR_COEFF0 |
| V_BLEND_RGB2YCBCR_COEFF5 | 0x000000A034 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_RGB2YCBCR_COEFF5:Description same as V_BLEND_RGB2YCBCR_COEFF0 |
| V_BLEND_RGB2YCBCR_COEFF6 | 0x000000A038 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_RGB2YCBCR_COEFF6:Description same as V_BLEND_RGB2YCBCR_COEFF0 |
| V_BLEND_RGB2YCBCR_COEFF7 | 0x000000A03C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_RGB2YCBCR_COEFF7:Description same as V_BLEND_RGB2YCBCR_COEFF0 |
| V_BLEND_RGB2YCBCR_COEFF8 | 0x000000A040 | 32 | mixedMixed types. See bit-field details. | 0x00001000 | V_BLEND_RGB2YCBCR_COEFF8:Description same as V_BLEND_RGB2YCBCR_COEFF0 |
| V_BLEND_IN1CSC_COEFF0 | 0x000000A044 | 32 | mixedMixed types. See bit-field details. | 0x00001000 | V_BLEND_IN1CSC_COEFF0:Coefficient values from Matrix for input color space convertor(video). A total of 9 values are needed to form 3x3 matrix. The value is scaled by 2^12 and stored in 15-bit signed format.(1bit reserved). 12Bits out of the 15 represent fractional value and 2 bits for decimal value and one signed bit. The order of programming values is from v0 - v8 |
| V_BLEND_IN1CSC_COEFF1 | 0x000000A048 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_IN1CSC_COEFF1:Description same as V_BLEND_IN1CSC_COEFF0 |
| V_BLEND_IN1CSC_COEFF2 | 0x000000A04C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_IN1CSC_COEFF2:Description same as V_BLEND_IN1CSC_COEFF0 |
| V_BLEND_IN1CSC_COEFF3 | 0x000000A050 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_IN1CSC_COEFF3:Description same as V_BLEND_IN1CSC_COEFF0 |
| V_BLEND_IN1CSC_COEFF4 | 0x000000A054 | 32 | mixedMixed types. See bit-field details. | 0x00001000 | V_BLEND_IN1CSC_COEFF4:Description same as V_BLEND_IN1CSC_COEFF0 |
| V_BLEND_IN1CSC_COEFF5 | 0x000000A058 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_IN1CSC_COEFF5:Description same as V_BLEND_IN1CSC_COEFF0 |
| V_BLEND_IN1CSC_COEFF6 | 0x000000A05C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_IN1CSC_COEFF6:Description same as V_BLEND_IN1CSC_COEFF0 |
| V_BLEND_IN1CSC_COEFF7 | 0x000000A060 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_IN1CSC_COEFF7:CDescription same as V_BLEND_IN1CSC_COEFF0 |
| V_BLEND_IN1CSC_COEFF8 | 0x000000A064 | 32 | mixedMixed types. See bit-field details. | 0x00001000 | V_BLEND_IN1CSC_COEFF8:Description same as V_BLEND_IN1CSC_COEFF0 |
| V_BLEND_LUMA_IN1CSC_OFFSET | 0x000000A068 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_LUMA_IN1CSC_OFFSET: Offset values for Y before and after matrix multiplication for input color space conversion |
| V_BLEND_CR_IN1CSC_OFFSET | 0x000000A06C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_CR_IN1CSC_OFFSET: Offset values for CR before and after matrix multiplication for input color space conversion |
| V_BLEND_CB_IN1CSC_OFFSET | 0x000000A070 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_CB_IN1CSC_OFFSET: Offset values for CB before and after matrix multiplication for input color space conversion |
| V_BLEND_LUMA_OUTCSC_OFFSET | 0x000000A074 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_LUMA_OUTCSC_OFFSET: Offset values for Y before and after matrix multiplication for output color space conversion |
| V_BLEND_CR_OUTCSC_OFFSET | 0x000000A078 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_CR_OUTCSC_OFFSET: Offset values for CR before and after matrix multiplication for output color space conversion |
| V_BLEND_CB_OUTCSC_OFFSET | 0x000000A07C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_CB_OUTCSC_OFFSET: Offset values for color CB before and after matrix multiplication for output color space conversion |
| V_BLEND_IN2CSC_COEFF0 | 0x000000A080 | 32 | mixedMixed types. See bit-field details. | 0x00001000 | V_BLEND_IN2CSC_COEFF0:Coefficient values from Matrix for input color space convertor(graphics). A total of 9 values are needed to form 3x3 matrix. The value is scaled by 2^12 and stored in 15-bit signed format.(1bit reserved). 12Bits out of the 15 represent fractional value and 2 bits for decimal value and one signed bit. The order of programming values is from v0 - v8 |
| V_BLEND_IN2CSC_COEFF1 | 0x000000A084 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_IN2CSC_COEFF1:Description same as V_BLEND_IN2CSC_COEFF0 |
| V_BLEND_IN2CSC_COEFF2 | 0x000000A088 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_IN2CSC_COEFF2:Description same as V_BLEND_IN2CSC_COEFF0 |
| V_BLEND_IN2CSC_COEFF3 | 0x000000A08C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_IN2CSC_COEFF3:Description same as V_BLEND_IN2CSC_COEFF0 |
| V_BLEND_IN2CSC_COEFF4 | 0x000000A090 | 32 | mixedMixed types. See bit-field details. | 0x00001000 | V_BLEND_IN2CSC_COEFF4:Description same as V_BLEND_IN2CSC_COEFF0 |
| V_BLEND_IN2CSC_COEFF5 | 0x000000A094 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_IN2CSC_COEFF5:Description same as V_BLEND_IN2CSC_COEFF0 |
| V_BLEND_IN2CSC_COEFF6 | 0x000000A098 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_IN2CSC_COEFF6:Description same as V_BLEND_IN2CSC_COEFF0 |
| V_BLEND_IN2CSC_COEFF7 | 0x000000A09C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_IN2CSC_COEFF7:Description same as V_BLEND_IN2CSC_COEFF0 |
| V_BLEND_IN2CSC_COEFF8 | 0x000000A0A0 | 32 | mixedMixed types. See bit-field details. | 0x00001000 | V_BLEND_IN2CSC_COEFF8:Description same as V_BLEND_IN2CSC_COEFF0 |
| V_BLEND_LUMA_IN2CSC_OFFSET | 0x000000A0A4 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_LUMA_IN2CSC_OFFSET: Offset values for Y before and after matrix multiplication for input color space conversion |
| V_BLEND_CR_IN2CSC_OFFSET | 0x000000A0A8 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_CR_IN2CSC_OFFSET: Offset values for CR before and after matrix multiplication for input color space conversion |
| V_BLEND_CB_IN2CSC_OFFSET | 0x000000A0AC | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_CB_IN2CSC_OFFSET: Offset values for CB before and after matrix multiplication for input color space conversion |
| V_BLEND_CHROMA_KEY_ENABLE | 0x000000A1D0 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_CHROMA_KEY_ENABLE |
| V_BLEND_CHROMA_KEY_COMP1 | 0x000000A1D4 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_CHROMA_KEY_COMP1: |
| V_BLEND_CHROMA_KEY_COMP2 | 0x000000A1D8 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_CHROMA_KEY_COMP2 |
| V_BLEND_CHROMA_KEY_COMP3 | 0x000000A1DC | 32 | mixedMixed types. See bit-field details. | 0x00000000 | V_BLEND_CHROMA_KEY_COMP3: [11:0]: B component of the key minimum value [27:16]: B component of the key maximum value |
| AV_BUF_FORMAT | 0x000000B000 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | AV_BUF_FORMAT: This register should be programmed based on the Video/Graphics packing format in memory. DP unpacker works based on this |
| AV_BUF_NON_LIVE_LATENCY | 0x000000B008 | 32 | mixedMixed types. See bit-field details. | 0x00000180 | The memory fetch latency. This parameter is used to offset the early VTC. The max latency supported is 412. This should have a buffer of 35 pixel clocks than actual maximum latency expected in the system |
| AV_CHBUF0 | 0x000000B010 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | AV_CHBUF0: Channel Enable, flush and Burst length to be programmed based on video formats. Each channel can be programmed with independent BL Channel 0: must be always enabled for any video mode. Channel 1 and 2: should be enabled for planar modes. Channel 3: for graphics. Channel 4 and 5: for audio modes |
| AV_CHBUF1 | 0x000000B014 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | AV_CHBUF1:Same as AV_CHBUF0 |
| AV_CHBUF2 | 0x000000B018 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | AV_CHBUF2:Same as AV_CHBUF0 |
| AV_CHBUF3 | 0x000000B01C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | AV_CHBUF3:Same as AV_CHBUF0 |
| AV_CHBUF4 | 0x000000B020 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | AV_CHBUF4 |
| AV_CHBUF5 | 0x000000B024 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | AV_CHBUF5: Same as AV_CHBUF4 |
| AV_BUF_STC_CONTROL | 0x000000B02C | 32 | rwNormal read/write | 0x00000000 | AV_BUF_STC_CONTROL: |
| AV_BUF_STC_INIT_VALUE0 | 0x000000B030 | 32 | rwNormal read/write | 0x00000000 | AV_BUF_STC_INIT_VALUE0: |
| AV_BUF_STC_INIT_VALUE1 | 0x000000B034 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | AV_BUF_STC_INIT_VALUE1: |
| AV_BUF_STC_ADJ | 0x000000B038 | 32 | rwNormal read/write | 0x00000000 | AV_BUF_STC_ADJ: A write to this register triggers STC adjust |
| AV_BUF_STC_VIDEO_VSYNC_TS_REG0 | 0x000000B03C | 32 | roRead-only | 0x00000000 | AV_BUF_STC_VIDEO_VSYNC_TS_REG0: STC TS with VSYNC event |
| AV_BUF_STC_VIDEO_VSYNC_TS_REG1 | 0x000000B040 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | AV_BUF_STC_VIDEO_VSYNC_TS_REG1: STC TS with VSYNC event |
| AV_BUF_STC_EXT_VSYNC_TS_REG0 | 0x000000B044 | 32 | roRead-only | 0x00000000 | AV_BUF_STC_EXT_VSYNC_TS_REG0: STC TS with external VSYNC event |
| AV_BUF_STC_EXT_VSYNC_TS_REG1 | 0x000000B048 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | AV_BUF_STC_EXT_VSYNC_TS_REG1: STC TS with VSYNC event |
| AV_BUF_STC_CUSTOM_EVENT_TS_REG0 | 0x000000B04C | 32 | roRead-only | 0x00000000 | AV_BUF_STC_CUSTOM_EVENT_TS_REG0: STC TS with custom event1 |
| AV_BUF_STC_CUSTOM_EVENT_TS_REG1 | 0x000000B050 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | AV_BUF_STC_CUSTOM_EVENT_TS_REG1: STC TS with custom event1 |
| AV_BUF_STC_CUSTOM_EVENT2_TS_REG0 | 0x000000B054 | 32 | roRead-only | 0x00000000 | AV_BUF_STC_CUSTOM_EVENT2_TS_REG0: STC TS with custom event 2 (can be audio TS) |
| AV_BUF_STC_CUSTOM_EVENT2_TS_REG1 | 0x000000B058 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | AV_BUF_STC_CUSTOM_EVENT2_TS_REG1: STC TS with custom event2 |
| AV_BUF_STC_SNAPSHOT0 | 0x000000B060 | 32 | roRead-only | 0x00000000 | AV_BUF_STC_SNAPSHOT0 |
| AV_BUF_STC_SNAPSHOT1 | 0x000000B064 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | AV_BUF_STC_SNAPSHOT1 |
| AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT | 0x000000B070 | 32 | mixedMixed types. See bit-field details. | 0x00000008 | AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT: to select the buffer manager outputs |
| AV_BUF_HCOUNT_VCOUNT_INT0 | 0x000000B074 | 32 | rwNormal read/write | 0x00000000 | AV_BUF_HCOUNT_VCOUNT_INT0: When the early VTC timing values(VCOUNT and HCOUNT) match the values programmed in this register and corresponding interrupt mask is enabled, an interrupt is generated |
| AV_BUF_HCOUNT_VCOUNT_INT1 | 0x000000B078 | 32 | rwNormal read/write | 0x00000000 | AV_BUF_HCOUNT_VCOUNT_INT1: When the early VTC timing values(VCOUNT and HCOUNT) match the values programmed in this register and corresponding interrupt mask is enabled, an interrupt is generated |
| AV_BUF_DITHER_CONFIG | 0x000000B07C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | This register is used for configuring dither functions |
| DITHER_CONFIG_SEED0 | 0x000000B080 | 32 | mixedMixed types. See bit-field details. | 0x00008000 | To set seed for LFSR0 |
| DITHER_CONFIG_SEED1 | 0x000000B084 | 32 | mixedMixed types. See bit-field details. | 0x00008080 | Description same as DITHER_CONFIG_SEED0 |
| DITHER_CONFIG_SEED2 | 0x000000B088 | 32 | mixedMixed types. See bit-field details. | 0x00008008 | Description same as DITHER_CONFIG_SEED0 |
| DITHER_CONFIG_MAX | 0x000000B08C | 32 | mixedMixed types. See bit-field details. | 0x00000FFF | To set the max output value on video pixel (at the blender output towards DP ) |
| DITHER_CONFIG_MIN | 0x000000B090 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | To set the min output value on video pixel (at the blender output towards DP ) |
| PATTERN_GEN_SELECT | 0x000000B100 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | PATTERN_GEN_SELECT:PATTERN_GEN_SELECT: |
| AUD_PATTERN_SELECT1 | 0x000000B104 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | AUD_CH1_PAT_SELECT |
| AUD_PATTERN_SELECT2 | 0x000000B108 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | AUD_CH2_PAT_SELECT |
| AV_BUF_AUD_VID_CLK_SOURCE | 0x000000B120 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | AV_BUF_AUD_VID_CLK_SOURCE: When live video from PL is absent, then the internal clock shall be video pipeline clock. If the live video is present, then clock from PL shall be the video pipe line clock. Similarly for the audio we can select from either PS or PL clock |
| AV_BUF_SRST_REG | 0x000000B124 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | AV_BUF_SRST_REG |
| AV_BUF_AUDIO_RDY_INTERVAL | 0x000000B128 | 32 | rwNormal read/write | 0x00000000 | AV_BUF_AUDIO_RDY_INTERVAL. Debug register. |
| AV_BUF_AUDIO_CH_CONFIG | 0x000000B12C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | AV_BUF_AUDIO_CH_CONFIG |
| AV_BUF_GRAPHICS_COMP0_SCALE_FACTOR | 0x000000B200 | 32 | mixedMixed types. See bit-field details. | 0x00010101 | Scaling factor for graphics for component 0 For 4-bits, scale factor will be 16/15*2^16 = 0x11111 For 5-bits, scale factor will be 32/31*2^16 = 0x10842 For 6-bits, scale factor will be 64/63*2^16 = 0x10410. For 8-bits, scale factor will be 256/255*2^16 = 0x10101 For 10-bits, scale factor will be 1024/1023*2^16 = 0x10040 For BPC =12, no scaling is done. This register is unused and can be default |
| AV_BUF_GRAPHICS_COMP1_SCALE_FACTOR | 0x000000B204 | 32 | mixedMixed types. See bit-field details. | 0x00010101 | Scaling factor for graphics for component1. Description same as AV_BUF_GRAPHICS_COMP0_SCALE_FACTOR |
| AV_BUF_GRAPHICS_COMP2_SCALE_FACTOR | 0x000000B208 | 32 | mixedMixed types. See bit-field details. | 0x00010101 | Scaling factor for graphics for component 2.Description same as AV_BUF_GRAPHICS_COMP0_SCALE_FACTOR |
| AV_BUF_VIDEO_COMP0_SCALE_FACTOR | 0x000000B20C | 32 | mixedMixed types. See bit-field details. | 0x00010101 | Scaling factor for video color comp0.Description same as AV_BUF_GRAPHICS_COMP0_SCALE_FACTOR |
| AV_BUF_VIDEO_COMP1_SCALE_FACTOR | 0x000000B210 | 32 | mixedMixed types. See bit-field details. | 0x00010101 | Scaling factor for video color comp1.Description same as AV_BUF_GRAPHICS_COMP0_SCALE_FACTOR |
| AV_BUF_VIDEO_COMP2_SCALE_FACTOR | 0x000000B214 | 32 | mixedMixed types. See bit-field details. | 0x00010101 | Scaling factor for video color comp2.Description same as AV_BUF_GRAPHICS_COMP0_SCALE_FACTOR |
| AV_BUF_LIVE_VIDEO_COMP0_SF | 0x000000B218 | 32 | mixedMixed types. See bit-field details. | 0x00010101 | Scaling factor for live video color comp0.Description same as AV_BUF_GRAPHICS_COMP0_SCALE_FACTOR |
| AV_BUF_LIVE_VIDEO_COMP1_SF | 0x000000B21C | 32 | mixedMixed types. See bit-field details. | 0x00010101 | Scaling factor for live video color comp1.Description same as AV_BUF_GRAPHICS_COMP0_SCALE_FACTOR |
| AV_BUF_LIVE_VIDEO_COMP2_SF | 0x000000B220 | 32 | mixedMixed types. See bit-field details. | 0x00010101 | Scaling factor for live video color comp2.Description same as AV_BUF_GRAPHICS_COMP0_SCALE_FACTOR |
| AV_BUF_LIVE_VID_CONFIG | 0x000000B224 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Programmable option to configure Cb or Cr first, when YUV422 mode is enabled |
| AV_BUF_LIVE_GFX_COMP0_SF | 0x000000B228 | 32 | mixedMixed types. See bit-field details. | 0x00010101 | Scaling factor for live graphics color comp0.Description same as AV_BUF_GRAPHICS_COMP0_SCALE_FACTOR |
| AV_BUF_LIVE_GFX_COMP1_SF | 0x000000B22C | 32 | mixedMixed types. See bit-field details. | 0x00010101 | Scaling factor for live graphics color comp1.Description same as AV_BUF_GRAPHICS_COMP0_SCALE_FACTOR |
| AV_BUF_LIVE_GFX_COMP2_SF | 0x000000B230 | 32 | mixedMixed types. See bit-field details. | 0x00010101 | Scaling factor for live graphics color comp2.Description same as AV_BUF_GRAPHICS_COMP0_SCALE_FACTOR |
| AV_BUF_LIVE_GFX_CONFIG | 0x000000B234 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Programmable option to configure Cb or Cr first, when YUV422 mode is enabled |
| AUDIO_MIXER_VOLUME_CONTROL | 0x000000C000 | 32 | rwNormal read/write | 0x00000000 | AUDIO_MIXER_VOLUME_CONTROL:Setting value to 8192 means no volume change (1.0 scaling factor) |
| AUDIO_MIXER_META_DATA | 0x000000C004 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | AUDIO_MIXER_META_DATA |
| AUD_CH_STATUS_REG0 | 0x000000C008 | 32 | rwNormal read/write | 0x00000000 | AUD_CH_STATUS_REG0: Audio Channel status bits 31 to 0 |
| AUD_CH_STATUS_REG1 | 0x000000C00C | 32 | rwNormal read/write | 0x00000000 | AUD_CH_STATUS_REG1: Audio Channel status bits 63 to 32 |
| AUD_CH_STATUS_REG2 | 0x000000C010 | 32 | rwNormal read/write | 0x00000000 | AUD_CH_STATUS_REG2: Audio Channel status bits 95 to 64 |
| AUD_CH_STATUS_REG3 | 0x000000C014 | 32 | rwNormal read/write | 0x00000000 | AUD_CH_STATUS_REG3: Audio Channel status bits 127 to 96 |
| AUD_CH_STATUS_REG4 | 0x000000C018 | 32 | rwNormal read/write | 0x00000000 | AUD_CH_STATUS_REG4: Audio Channel status bits 159 to 128 |
| AUD_CH_STATUS_REG5 | 0x000000C01C | 32 | rwNormal read/write | 0x00000000 | AUD_CH_STATUS_REG5: Audio Channel status bits 191 to 160 |
| AUD_CH_A_DATA_REG0 | 0x000000C020 | 32 | rwNormal read/write | 0x00000000 | AUD_CH_A_DATA_REG0: User data bits 31 to 0 |
| AUD_CH_A_DATA_REG1 | 0x000000C024 | 32 | rwNormal read/write | 0x00000000 | AUD_CH_A_DATA_REG1: User data bits 63 to 32 |
| AUD_CH_A_DATA_REG2 | 0x000000C028 | 32 | rwNormal read/write | 0x00000000 | AUD_CH_A_DATA_REG2: User data bits 95 to 64 |
| AUD_CH_A_DATA_REG3 | 0x000000C02C | 32 | rwNormal read/write | 0x00000000 | AUD_CH_A_DATA_REG3: User data bits 127 to 96 |
| AUD_CH_A_DATA_REG4 | 0x000000C030 | 32 | rwNormal read/write | 0x00000000 | AUD_CH_A_DATA_REG4: User data bits 159 to 128 |
| AUD_CH_A_DATA_REG5 | 0x000000C034 | 32 | rwNormal read/write | 0x00000000 | AUD_CH_A_DATA_REG5: User data bits 191 to 160 |
| AUD_CH_B_DATA_REG0 | 0x000000C038 | 32 | rwNormal read/write | 0x00000000 | AUD_CH_B_DATA_REG0: User data bits 31 to 0. |
| AUD_CH_B_DATA_REG1 | 0x000000C03C | 32 | rwNormal read/write | 0x00000000 | AUD_CH_B_DATA_REG1: User data bits 63 to 32. |
| AUD_CH_B_DATA_REG2 | 0x000000C040 | 32 | rwNormal read/write | 0x00000000 | AUD_CH_B_DATA_REG2: User data bits 95 to 64. |
| AUD_CH_B_DATA_REG3 | 0x000000C044 | 32 | rwNormal read/write | 0x00000000 | AUD_CH_B_DATA_REG3: User data bits 127 to 96. |
| AUD_CH_B_DATA_REG4 | 0x000000C048 | 32 | rwNormal read/write | 0x00000000 | AUD_CH_B_DATA_REG4: User data bits 159 to 128. |
| AUD_CH_B_DATA_REG5 | 0x000000C04C | 32 | rwNormal read/write | 0x00000000 | AUD_CH_B_DATA_REG5: User data bits 191 to 160. |
| AUDIO_SOFT_RESET | 0x000000CC00 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Audio Soft reset reigster. |
| PATGEN_CRC_R | 0x000000CC10 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | 16 bit CRC calculated on the first component of video output from Internal Test Pattern Generator |
| PATGEN_CRC_G | 0x000000CC14 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | 16 bit CRC calculated on the second component of video output from Internal Test Pattern Generator |
| PATGEN_CRC_B | 0x000000CC18 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | 16 bit CRC calculated on the third component of video output from Internal Test Pattern Generator |