DMA_CHANNEL_AXI_INTERRUPT_CONTROL (AXIPCIE_DMA) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DMA_CHANNEL_AXI_INTERRUPT_CONTROL (AXIPCIE_DMA) Register Description

Register NameDMA_CHANNEL_AXI_INTERRUPT_CONTROL
Offset Address0x0000000068
Absolute Address 0x00FD0F0068 (AXIPCIE_DMA0)
0x00FD0F00E8 (AXIPCIE_DMA1)
0x00FD0F0168 (AXIPCIE_DMA2)
0x00FD0F01E8 (AXIPCIE_DMA3)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionPCI Express Interrupt Control

DMA_CHANNEL_AXI_INTERRUPT_CONTROL (AXIPCIE_DMA) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:24roRead-only0x0
coalesce_count23:16rwNormal read/write0x0AXI DMA SGL Interrupt Coalesce Count. Controls the frequency at which a DMA SGL Interrupt Event (completion of a source SGL Element that had both the EOP and Interrupt SGL control bits set to 1) causes AXI Interrupts. An internal DMA Channel-specific AXI DMA SGL Coalesce Counter is maintained. For each DMA SGL Interrupt Event, if the current AXI DMA SGL Coalesce Counter is equal to AXI DMA SGL Interrupt Coalesce Count, then a AXI interrupt is generated and the AXI DMA SGL Coalesce Counter is cleared otherwise the AXI DMA SGL Coalesce Counter is incremented. The AXI DMA SGL Coalesce Counter is also cleared when DMA Enable == 0. This mechanism allows software to configure the DMA Channel to interrupt AXI once every 1-256 DMA SGL Interrupt Events. When a non-0 value is programmed into AXI DMA SGL Interrupt Coalesce Count, software must anticipate that at the end of all DMA packet transfers, interrupts may be pending in the AXI DMA SGL Coalesce Counter that will not cause an interrupt because no more interrupts will arrive for AXI DMA SGL Coalesce Counter to reach the AXI DMA SGL Interrupt Coalesce Count threshold.
Reserved15:3roRead-only0x0
sgl_int_enable 2rwNormal read/write0x0AXI Enable DMA SGL Interrupt Event
dma_err_int_enable 1rwNormal read/write0x0AXI Enable DMA Error Interrupt Event
interrupt_enable 0rwNormal read/write0x0AXI Interrupt Enable