DMA_CHANNEL_AXI_INTERRUPT_CONTROL (AXIPCIE_DMA) Register Description
Register Name | DMA_CHANNEL_AXI_INTERRUPT_CONTROL |
---|---|
Offset Address | 0x0000000068 |
Absolute Address |
0x00FD0F0068 (AXIPCIE_DMA0) 0x00FD0F00E8 (AXIPCIE_DMA1) 0x00FD0F0168 (AXIPCIE_DMA2) 0x00FD0F01E8 (AXIPCIE_DMA3) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | PCI Express Interrupt Control |
DMA_CHANNEL_AXI_INTERRUPT_CONTROL (AXIPCIE_DMA) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:24 | roRead-only | 0x0 | |
coalesce_count | 23:16 | rwNormal read/write | 0x0 | AXI DMA SGL Interrupt Coalesce Count. Controls the frequency at which a DMA SGL Interrupt Event (completion of a source SGL Element that had both the EOP and Interrupt SGL control bits set to 1) causes AXI Interrupts. An internal DMA Channel-specific AXI DMA SGL Coalesce Counter is maintained. For each DMA SGL Interrupt Event, if the current AXI DMA SGL Coalesce Counter is equal to AXI DMA SGL Interrupt Coalesce Count, then a AXI interrupt is generated and the AXI DMA SGL Coalesce Counter is cleared otherwise the AXI DMA SGL Coalesce Counter is incremented. The AXI DMA SGL Coalesce Counter is also cleared when DMA Enable == 0. This mechanism allows software to configure the DMA Channel to interrupt AXI once every 1-256 DMA SGL Interrupt Events. When a non-0 value is programmed into AXI DMA SGL Interrupt Coalesce Count, software must anticipate that at the end of all DMA packet transfers, interrupts may be pending in the AXI DMA SGL Coalesce Counter that will not cause an interrupt because no more interrupts will arrive for AXI DMA SGL Coalesce Counter to reach the AXI DMA SGL Interrupt Coalesce Count threshold. |
Reserved | 15:3 | roRead-only | 0x0 | |
sgl_int_enable | 2 | rwNormal read/write | 0x0 | AXI Enable DMA SGL Interrupt Event |
dma_err_int_enable | 1 | rwNormal read/write | 0x0 | AXI Enable DMA Error Interrupt Event |
interrupt_enable | 0 | rwNormal read/write | 0x0 | AXI Interrupt Enable |