DMA_CHANNEL_AXI_INTERRUPT_STATUS (AXIPCIE_DMA) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DMA_CHANNEL_AXI_INTERRUPT_STATUS (AXIPCIE_DMA) Register Description

Register NameDMA_CHANNEL_AXI_INTERRUPT_STATUS
Offset Address0x000000006C
Absolute Address 0x00FD0F006C (AXIPCIE_DMA0)
0x00FD0F00EC (AXIPCIE_DMA1)
0x00FD0F016C (AXIPCIE_DMA2)
0x00FD0F01EC (AXIPCIE_DMA3)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionAXI Interrupt Status

DMA_CHANNEL_AXI_INTERRUPT_STATUS (AXIPCIE_DMA) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:4roRead-only0x0
software_int 3wtcReadable, write a 1 to clear0x0AXI Software Interrupt Status.
dma_sgl_int 2wtcReadable, write a 1 to clear0x0AXI DMA SGL Interrupt Status.
dma_error_int 1wtcReadable, write a 1 to clear0x0AXI DMA Error Interrupt Status.
Reserved 0roRead-only0x0