DMA_CHANNEL_DMA_STATUS (AXIPCIE_DMA) Register Description
| Register Name | DMA_CHANNEL_DMA_STATUS |
|---|---|
| Offset Address | 0x000000007C |
| Absolute Address |
0x00FD0F007C (AXIPCIE_DMA0) 0x00FD0F00FC (AXIPCIE_DMA1) 0x00FD0F017C (AXIPCIE_DMA2) 0x00FD0F01FC (AXIPCIE_DMA3) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00008000 |
| Description | DMA Channel Status |
DMA_CHANNEL_DMA_STATUS (AXIPCIE_DMA) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:16 | roRead-only | 0x0 | |
| channel_present | 15 | roRead-only | 0x1 | DMA Channel Present. During initialization, the DMA Driver can read this register at all possible DMA Channel Register locations to determine how many DMA Channels are implemented. |
| Reserved | 14 | roRead-only | 0x0 | |
| channel_number | 13:4 | roRead-only | 0x0 | DMA Channel Number[9:0]. Unique DMA Channel Number assigned to this DMA Channel. The DMA Channel Number register is for informational purposes and is not needed for DMA operation. DMA Channel number is unique for each DMA Channel even for multi-function and SR-IOV applications. |
| Reserved | 3:1 | roRead-only | 0x0 | |
| dma_running | 0 | roRead-only | 0x0 | DMA Running. Prior to transitioning DMA Enable from 0 to 1 or modifying the contents of the DMA Channels Queue Management Registers, software must read DMA Running == 0 to verify that the prior DMA operation completed and that it is safe to re-initialize and re-start the DMA Channel. The DMA Channel Source and Destination Queues can be re-used for new DMA operations (by changing the Queue Scatter-Gather List contents) without having to disable the DMA Channel. In general software should setup the Source SGL, Destination SGL, Source DMA Completion Status, and Destination DMA Completion Status Queues once at driver initialization and keep the DMA Channel Enabled for the entire time the driver is loaded. When there is new work to do, the Driver makes the associated queue elements available to be executed by updatign the Queue LIMIT pointers. |