DMA_CHANNEL_DST_Q_LIMIT (AXIPCIE_DMA) Register Description
| Register Name | DMA_CHANNEL_DST_Q_LIMIT |
|---|---|
| Offset Address | 0x000000001C |
| Absolute Address |
0x00FD0F001C (AXIPCIE_DMA0) 0x00FD0F009C (AXIPCIE_DMA1) 0x00FD0F011C (AXIPCIE_DMA2) 0x00FD0F019C (AXIPCIE_DMA3) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Queue Limit Pointer |
DMA_CHANNEL_DST_Q_LIMIT (AXIPCIE_DMA) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| limit | 31:0 | rwNormal read/write | 0x0 | Queue Flow Control - Limit Pointer. Index of the first Queue element still ``owned by software. Incremented by software to give the DMA Channel additional elements to execute. DMA Channel hardware will pause and not utilize queue elements when Q_LIMIT is reached until Q_LIMIT is advanced to provide additional elements to execute. |