DMA_CHANNEL_DST_Q_SIZE (AXIPCIE_DMA) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DMA_CHANNEL_DST_Q_SIZE (AXIPCIE_DMA) Register Description

Register NameDMA_CHANNEL_DST_Q_SIZE
Offset Address0x0000000018
Absolute Address 0x00FD0F0018 (AXIPCIE_DMA0)
0x00FD0F0098 (AXIPCIE_DMA1)
0x00FD0F0118 (AXIPCIE_DMA2)
0x00FD0F0198 (AXIPCIE_DMA3)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionQueue Size

DMA_CHANNEL_DST_Q_SIZE (AXIPCIE_DMA) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
queue_size31:0rwNormal read/write0x0Queue Size. Number of Elements in the Queue. queue_size must be >= 2. A minimum of 2 elements is required to support software/hardware queue flow control ownership. queue_size is used to identify the wrap boundary of the Queue.