DMA_CHANNEL_PCIE_INTERRUPT_ASSERT (AXIPCIE_DMA) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DMA_CHANNEL_PCIE_INTERRUPT_ASSERT (AXIPCIE_DMA) Register Description

Register NameDMA_CHANNEL_PCIE_INTERRUPT_ASSERT
Offset Address0x0000000070
Absolute Address 0x00FD0F0070 (AXIPCIE_DMA0)
0x00FD0F00F0 (AXIPCIE_DMA1)
0x00FD0F0170 (AXIPCIE_DMA2)
0x00FD0F01F0 (AXIPCIE_DMA3)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionPCIe Interrupt Assertion.

DMA_CHANNEL_PCIE_INTERRUPT_ASSERT (AXIPCIE_DMA) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:4roRead-only0x0
pcie_software_interrupt 3rwNormal read/write0x0PCIe Software Interrupt. Write a 1 to this register to generate a PCIe Software Interrupt. An interrupt is generated and propagated through the PCI Express Core to PCIe in the same manner as a DMA Channel interrupt (using the same Interrupt Vector). Interrupts are generated by writes to this register independent of whether the DMA Channel is enabled.
Reserved 2:0roRead-only0x0