DMA_CHANNEL_SCRATCH0 (AXIPCIE_DMA) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DMA_CHANNEL_SCRATCH0 (AXIPCIE_DMA) Register Description

Register NameDMA_CHANNEL_SCRATCH0
Offset Address0x0000000050
Absolute Address 0x00FD0F0050 (AXIPCIE_DMA0)
0x00FD0F00D0 (AXIPCIE_DMA1)
0x00FD0F0150 (AXIPCIE_DMA2)
0x00FD0F01D0 (AXIPCIE_DMA3)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionScratchpad Register

DMA_CHANNEL_SCRATCH0 (AXIPCIE_DMA) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
scratch031:0rwNormal read/write0x0Scratchpad Register. Intended to enable information to be passed between sofwtare. For example, applications with both an AXI CPU and an PCIe CPU may use this register to pass information between CPUs. The DMA Channel implementation does not use or alter this information.