DMA_CHANNEL_SRC_Q_PTR_LO (AXIPCIE_DMA) Register Description
| Register Name | DMA_CHANNEL_SRC_Q_PTR_LO |
|---|---|
| Offset Address | 0x0000000000 |
| Absolute Address |
0x00FD0F0000 (AXIPCIE_DMA0) 0x00FD0F0080 (AXIPCIE_DMA1) 0x00FD0F0100 (AXIPCIE_DMA2) 0x00FD0F0180 (AXIPCIE_DMA3) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Queue Base Address Low |
DMA_CHANNEL_SRC_Q_PTR_LO (AXIPCIE_DMA) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| start_addr_lo | 31:6 | rwNormal read/write | 0x0 | Queue Base Address[31:6]. Queues are required to be 64-byte aligned (start_addr_lo[5:0] == 00000). |
| read_attr | 5:2 | rwNormal read/write | 0x0 | Queue Read Attributes. Transaction attributes used for Queue Reads. If Queue Location == AXI, read_attr[3:0] is used for m_arcache[3:0]. If Queue Location == PCIe, read_attr[2:0] is used for PCIe Attr[2:0]. |
| queue_enable | 1 | rwNormal read/write | 0x0 | Queue Enable |
| queue_location | 0 | rwNormal read/write | 0x0 | Queue Location |