DMA_CHANNEL_STAD_Q_PTR_HI (AXIPCIE_DMA) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DMA_CHANNEL_STAD_Q_PTR_HI (AXIPCIE_DMA) Register Description

Register NameDMA_CHANNEL_STAD_Q_PTR_HI
Offset Address0x0000000034
Absolute Address 0x00FD0F0034 (AXIPCIE_DMA0)
0x00FD0F00B4 (AXIPCIE_DMA1)
0x00FD0F0134 (AXIPCIE_DMA2)
0x00FD0F01B4 (AXIPCIE_DMA3)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionQueue Base Address High

DMA_CHANNEL_STAD_Q_PTR_HI (AXIPCIE_DMA) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
start_addr_hi31:0rwNormal read/write0x0Queue Base Address[63:32]. Must be set to 0x0 if the Queue is located in 32-bit address space.