DMA_CHANNEL_STAS_Q_NEXT (AXIPCIE_DMA) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DMA_CHANNEL_STAS_Q_NEXT (AXIPCIE_DMA) Register Description

Register NameDMA_CHANNEL_STAS_Q_NEXT
Offset Address0x0000000048
Absolute Address 0x00FD0F0048 (AXIPCIE_DMA0)
0x00FD0F00C8 (AXIPCIE_DMA1)
0x00FD0F0148 (AXIPCIE_DMA2)
0x00FD0F01C8 (AXIPCIE_DMA3)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionQueue Next Pointer

DMA_CHANNEL_STAS_Q_NEXT (AXIPCIE_DMA) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
next31:0rwNormal read/write0x0Queue Flow Control - Next Pointer. Index of the next Queue element that will be written by DMA Channel hardware with DMA completion status. Incremented by DMA Channel hardware as elements are reserved to receive DMA completion status. The number of queue elements available for the DMA Channel == STAS_Q_LIMIT - STAS_Q_NEXT (taking into account wrapping). STAS_Q_NEXT does not indicate that Queue Elements have been written, only that the DMA Channel has reserved elements to receive DMA completion status. Software must write this register to 0x0 to initialize the queue prior to enabling the DMA Channel. Software is prohibited from writing this register while the DMA Channel is enabled. STAS_Q_NEXT is utilized by DMA Channel hardware to track its location in the queue and should not be used by DMA software.