| Register Name | Offset Address | Width | Type | Reset Value | Description |
|---|
| DPDMA_ERR_CTRL | 0x0000000000 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Enable/Disable a error response |
| DPDMA_ISR | 0x0000000004 | 32 | wtcReadable, write a 1 to clear | 0x00000000 | Interrupt Status Register for intrN. This is a sticky register that holds the value of the interrupt until cleared by a value of 1. |
| DPDMA_IMR | 0x0000000008 | 32 | roRead-only | 0x0FFFFFFF | Interrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER. |
| DPDMA_IEN | 0x000000000C | 32 | woWrite-only | 0x00000000 | Interrupt Enable Register. A write of 1 to this location will unmask the interrupt. (IMR: 0) |
| DPDMA_IDS | 0x0000000010 | 32 | woWrite-only | 0x00000000 | Interrupt Disable Register. A write of 1 one to this location will mask the interrupt. (IMR: 1) |
| DPDMA_EISR | 0x0000000014 | 32 | wtcReadable, write a 1 to clear | 0x00000000 | Interrupt Status Register for intrN. This is a sticky register that holds the value of the interrupt until cleared by a value of 1. |
| DPDMA_EIMR | 0x0000000018 | 32 | roRead-only | 0xFFFFFFFF | Interrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER. |
| DPDMA_EIEN | 0x000000001C | 32 | woWrite-only | 0x00000000 | Interrupt Enable Register. A write of 1 to this location will unmask the interrupt. (IMR: 0) |
| DPDMA_EIDS | 0x0000000020 | 32 | woWrite-only | 0x00000000 | Interrupt Disable Register. A write of one to this location will mask the interrupt. (IMR: 1) |
| DPDMA_CNTL | 0x0000000100 | 32 | razRead as zero | 0x00000000 | DPDMA Global control register, holds fields which control all 6 channels |
| DPDMA_GBL | 0x0000000104 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Global control register provides control to start or redirect any channel |
| DPDMA_ALC0_CNTL | 0x0000000108 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Global control register provides control to start or redirect any channel |
| DPDMA_ALC0_STATUS | 0x000000010C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Status Register |
| DPDMA_ALC0_MAX | 0x0000000110 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | ALC0 Max latency Register |
| DPDMA_ALC0_MIN | 0x0000000114 | 32 | mixedMixed types. See bit-field details. | 0x0000FFFF | ALC0 Min Latency Register |
| DPDMA_ALC0_ACC | 0x0000000118 | 32 | roRead-only | 0x00000000 | ALC0 Accumulated Transaction Latency Register |
| DPDMA_ALC0_ACC_TRAN | 0x000000011C | 32 | roRead-only | 0x00000000 | ALC1 Accumulated Transaction Count Register |
| DPDMA_ALC1_CNTL | 0x0000000120 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Global control register provides control to start or redirect any channel |
| DPDMA_ALC1_STATUS | 0x0000000124 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Status Register |
| DPDMA_ALC1_MAX | 0x0000000128 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | ALC1 Max latency Register |
| DPDMA_ALC1_MIN | 0x000000012C | 32 | mixedMixed types. See bit-field details. | 0x0000FFFF | ALC1 Min Latency Register |
| DPDMA_ALC1_ACC | 0x0000000130 | 32 | roRead-only | 0x00000000 | ALC1 Accumulated Transaction Latency Register |
| DPDMA_ALC1_ACC_TRAN | 0x0000000134 | 32 | roRead-only | 0x00000000 | ALC1 Accumulated Transaction Count Register |
| DPDMA_CH0_DSCR_STRT_ADDRE | 0x0000000200 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Descriptor Start Address Extension Register |
| DPDMA_CH0_DSCR_STRT_ADDR | 0x0000000204 | 32 | rwNormal read/write | 0x00000000 | Descriptor Start Address Register |
| DPDMA_CH0_CNTL | 0x0000000218 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Channel 0 Control Register |
| DPDMA_CH1_DSCR_STRT_ADDRE | 0x0000000300 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Descriptor Start Address Extension Register |
| DPDMA_CH1_DSCR_STRT_ADDR | 0x0000000304 | 32 | rwNormal read/write | 0x00000000 | Descriptor Start Address Register |
| DPDMA_CH1_CNTL | 0x0000000318 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Channel 1 Control Register |
| DPDMA_CH2_DSCR_STRT_ADDRE | 0x0000000400 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Descriptor Start Address Extension Register |
| DPDMA_CH2_DSCR_STRT_ADDR | 0x0000000404 | 32 | rwNormal read/write | 0x00000000 | Descriptor Start Address Register |
| DPDMA_CH2_CNTL | 0x0000000418 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Channel 2 Control Register |
| DPDMA_CH3_DSCR_STRT_ADDRE | 0x0000000500 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Descriptor Start Address Extension Register |
| DPDMA_CH3_DSCR_STRT_ADDR | 0x0000000504 | 32 | rwNormal read/write | 0x00000000 | Descriptor Start Address Register |
| DPDMA_CH3_CNTL | 0x0000000518 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Channel 3 Control Register |
| DPDMA_CH4_DSCR_STRT_ADDRE | 0x0000000600 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Descriptor Start Address Extension Register |
| DPDMA_CH4_DSCR_STRT_ADDR | 0x0000000604 | 32 | rwNormal read/write | 0x00000000 | Descriptor Start Address Register |
| DPDMA_CH4_CNTL | 0x0000000618 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Channel 4 Control Register |
| DPDMA_CH5_DSCR_STRT_ADDRE | 0x0000000700 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Descriptor Start Address Extension Register |
| DPDMA_CH5_DSCR_STRT_ADDR | 0x0000000704 | 32 | rwNormal read/write | 0x00000000 | Descriptor Start Address Register |
| DPDMA_CH5_CNTL | 0x0000000718 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Channel 4 Control Register |