DPDMA_ALC1_ACC (DPDMA) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DPDMA_ALC1_ACC (DPDMA) Register Description

Register NameDPDMA_ALC1_ACC
Offset Address0x0000000130
Absolute Address 0x00FD4C0130 (DPDMA)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionALC1 Accumulated Transaction Latency Register

DPDMA_ALC1_ACC (DPDMA) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
latency31:0roRead-only0x0Accumulated trnasaction latecy since last enable