DPDMA_ALC1_CNTL (DPDMA) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DPDMA_ALC1_CNTL (DPDMA) Register Description

Register NameDPDMA_ALC1_CNTL
Offset Address0x0000000120
Absolute Address 0x00FD4C0120 (DPDMA)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionGlobal control register provides control to start or redirect any channel

DPDMA_ALC1_CNTL (DPDMA) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:6razRead as zero0x0Reseved for future use
MON_ID 5:2rwNormal read/write0x0ALC uses this ID to filter the traffic on AXI channel and calculates latency number
CLEAR 1woWrite-only0x0this bit will clear the state of ALC
EN 0rwNormal read/write0x0Enable bit for ALC1
1: ALC is enable, it is calculating Min , Max and Ave
0: ALC is disable, it preserves the previous state untill "ALC Clear