DPDMA_ALC1_MAX (DPDMA) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DPDMA_ALC1_MAX (DPDMA) Register Description

Register NameDPDMA_ALC1_MAX
Offset Address0x0000000128
Absolute Address 0x00FD4C0128 (DPDMA)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionALC1 Max latency Register

DPDMA_ALC1_MAX (DPDMA) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:16razRead as zero0x0Reseved for future use
latency15:0roRead-only0x0Indicates maximum trnasaction latency logged since last clear