DPDMA_ALC1_MIN (DPDMA) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DPDMA_ALC1_MIN (DPDMA) Register Description

Register NameDPDMA_ALC1_MIN
Offset Address0x000000012C
Absolute Address 0x00FD4C012C (DPDMA)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x0000FFFF
DescriptionALC1 Min Latency Register

DPDMA_ALC1_MIN (DPDMA) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:16razRead as zero0x0Reseved for future use
latency15:0roRead-only0xFFFFIndicates minimum transaction latency logged since last clear